library verilog;use verilog.vl_types.all;entity \buffer\ is    port(        clk             : in     vl_logic;        dina_r          : in     vl_logic_vector(31 downto 0);        dina_i          : in     vl_logic_vector(31 downto 0);        dinb_r          : in     vl_logic_vector(31 downto 0);        dinb_i          : in     vl_logic_vector(31 downto 0);        cs              : in     vl_logic_vector(31 downto 0);        douta_r         : out    vl_logic_vector(31 downto 0);        douta_i         : out    vl_logic_vector(31 downto 0);        doutb_r         : out    vl_logic_vector(31 downto 0);        doutb_i         : out    vl_logic_vector(31 downto 0)    );end \buffer\;