library verilog;use verilog.vl_types.all;entity hjj is    port(        addr            : in     vl_logic_vector(12 downto 0);        clk             : in     vl_logic;        din             : in     vl_logic_vector(9 downto 0);        dout            : out    vl_logic_vector(9 downto 0);        en              : in     vl_logic;        we              : in     vl_logic    );end hjj;