library verilog;use verilog.vl_types.all;entity toptop is    port(        clk             : in     vl_logic;        RST             : in     vl_logic;        reset           : out    vl_logic;        fftin_r         : out    vl_logic_vector(15 downto 0);        fftin_i         : out    vl_logic_vector(15 downto 0);        ramouta1_r      : out    vl_logic_vector(31 downto 0);        ramouta1_i      : out    vl_logic_vector(31 downto 0);        start           : out    vl_logic;        finish          : out    vl_logic;        addr_con        : out    vl_logic_vector(9 downto 0);        addr1_a         : out    vl_logic_vector(9 downto 0);        addr1_b         : out    vl_logic_vector(9 downto 0);        addr2_a         : out    vl_logic_vector(9 downto 0);        addr2_b         : out    vl_logic_vector(9 downto 0);        wea1            : out    vl_logic;        dina_r          : out    vl_logic_vector(31 downto 0);        dina_i          : out    vl_logic_vector(31 downto 0);        dinb_r          : out    vl_logic_vector(31 downto 0);        dinb_i          : out    vl_logic_vector(31 downto 0);        douta_r         : out    vl_logic_vector(31 downto 0);        douta_i         : out    vl_logic_vector(31 downto 0);        doutb_r         : out    vl_logic_vector(31 downto 0);        doutb_i         : out    vl_logic_vector(31 downto 0);        cs              : out    vl_logic_vector(31 downto 0);        count1024       : out    vl_logic_vector(10 downto 0);        flag            : out    vl_logic;        count10         : out    vl_logic_vector(3 downto 0);        done            : out    vl_logic    );end toptop;