library verilog;use verilog.vl_types.all;entity get_cs is    port(        clk             : in     vl_logic;        reset           : in     vl_logic;        count10         : in     vl_logic_vector(3 downto 0);        full            : in     vl_logic;        done            : in     vl_logic;        cs              : out    vl_logic_vector(31 downto 0)    );end get_cs;