?? _primary.vhd
字號:
library verilog;use verilog.vl_types.all;entity converse is port( clk : in vl_logic; ce : in vl_logic; reset : in vl_logic; done : in vl_logic; start_t : in vl_logic; finish : out vl_logic; addr_con : out vl_logic_vector(9 downto 0); count1024 : out vl_logic_vector(10 downto 0); flag : out vl_logic );end converse;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -