?? pc.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pc is
port(d_mb :in std_logic_vector(7 downto 0);
ld_mb,clk,reset,increment:in std_logic;
pc :buffer std_logic_vector(7 downto 0));
end pc;
architecture a of pc is
begin
process(clk,reset)
begin
if clk'event and clk='1' then
if reset='1' then
pc<="00000000";
end if;
if ld_mb='1' then
pc<=d_mb;
elsif increment='1' then
pc<=pc+1;
end if;
end if;
end process;
end a;
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