set -xsthdpdir D:/Verilog/TINY3/xst\
set -checkcmdline no
run -ifn TINY_TOP.prj -ifmt mixed -ofn TINY_TOP -ofmt NGC -p xc3s500e-4-fg320 -top TINY_TOP -opt_mode Speed -opt_level 1 -iuc NO -lso TINY_TOP.lso -keep_hierarchy NO -netlist_hierarchy as_optimized -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -bram_utilization_ratio 100 -verilog2001 YES -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -auto_bram_packing NO -mux_extract YES -resource_sharing YES -async_to_sync NO -mult_style auto -iobuf YES -max_fanout 500 -bufg 24 -register_duplication YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 -crit Speed -opt_level_power 1 -mapstyle lut -fsm_encoding Auto -t XILINX -addsub_extract yes