///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_v4_dqs_iob.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Places the data stobes in the IOBs.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module mem_interface_top_v4_dqs_iob
  (
   input        CLK,
   input        DLYINC,
   input        DLYCE,
   input        DLYRST,
   input        CTRL_DQS_RST,
   input        CTRL_DQS_EN,
   inout        DDR_DQS,
   output       DQS_RISE
   );

   wire         dqs_in;
   wire         dqs_out;
   wire         dqs_delayed;
   wire         ctrl_dqs_en_r1;
   wire         vcc;
   wire         gnd;
   wire         clk180;
   wire         dqs_int;
   reg          data1;


   assign       vcc         = 1'b1;
   assign       gnd         = 1'b0;
   assign       clk180      = ~CLK;


   always @ (posedge clk180) begin
      if (CTRL_DQS_RST == 1'b1)
        data1 <= 1'b0;
      else
        data1 <= 1'b1;
   end


   defparam idelay_dqs.IOBDELAY_TYPE = "VARIABLE";
   defparam idelay_dqs.IOBDELAY_VALUE = 0;

   IDELAY idelay_dqs
     (
      .O   (dqs_delayed),
      .I   (dqs_in),
      .C   (CLK),
      .CE  (DLYCE),
      .INC (DLYINC),
      .RST (DLYRST)
      );

   FD dqs_pipe1
     (
      .D (dqs_delayed),
      .Q (dqs_int),
      .C (CLK)
      );


   FD dqs_pipe2
     (
      .D (dqs_int),
      .Q (DQS_RISE),
      .C (CLK)
      );


   defparam oddr_dqs.SRTYPE = "SYNC";
   defparam oddr_dqs.DDR_CLK_EDGE = "OPPOSITE_EDGE";

   ODDR oddr_dqs
     (
      .Q      (dqs_out),
      .C      (clk180),
      .CE     (vcc),
      .D1     (data1),
      .D2     (gnd),
      .R      (gnd),
      .S      (gnd)
      );

   FD tri_state_dqs
     (
      .D      (CTRL_DQS_EN),
      .Q      (ctrl_dqs_en_r1),
      .C      (clk180)
      );


   IOBUF iobuf_dqs
     (
      .I      (dqs_out),
      .T      (ctrl_dqs_en_r1),
      .IO     (DDR_DQS),
      .O      (dqs_in)
      );


endmodule