///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_main_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: The main design logic is instantiated here which includes the
//              test bench and the user interface also. It takes the memory
//              signals and the calibrated clocks and the reset signals from
//              the DCM.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_main_0
  (
   input                                clk_0,
   input                                clk_90,
   input                                sys_rst,
   input                                sys_rst90,
   input                                idelay_ctrl_rdy,
   inout   [`data_width-1:0]            DDR_DQ,
   inout   [`data_strobe_width-1:0]     DDR_DQS,
   output[`data_mask_width-1:0]           DDR_DM,
 
   
   output                               DDR_RAS_N,
   output                               DDR_CAS_N,
   output                               DDR_WE_N,
   output  [`cke_width-1:0]             DDR_CKE,
   output  [`no_of_cs-1:0]              DDR_CS_N,
   output  [`clk_width-1:0]             DDR_CK,
   output  [`clk_width-1:0]             DDR_CK_N,
   output  [`bank_address-1:0]          DDR_BA,
   output  [`row_address-1:0]           DDR_A,
   output                               init_done,
   output                               ERROR
   );

   wire [35:0]                          app_af_addr;
   wire                                 app_af_wren;
   wire [(`data_width*2)-1:0]           app_wr_df_data;
   wire [(`data_mask_width*2)-1:0]      app_mask_df_data;
   wire                                 app_wr_df_wren;
   wire                                 wr_df_almost_full;
   wire                                 rd_data_valid;
   wire [(`data_width*2)-1:0]           rd_data_fifo_out;
   wire [2:0]                           burst_length;
   wire                                 clk_tb;
   wire                                 reset_tb;
   wire                                 af_almost_full;

   mem_interface_top_top_0 top_00
     (
      .clk_0                         (clk_0),
      .clk_90                        (clk_90),
      .sys_rst                       (sys_rst),
      .sys_rst90                     (sys_rst90),
      .idelay_ctrl_rdy               (idelay_ctrl_rdy),
      .DDR_RAS_N                     (DDR_RAS_N),
      .DDR_CAS_N                     (DDR_CAS_N),
      .DDR_WE_N                      (DDR_WE_N),
      .DDR_CKE                       (DDR_CKE),
      .DDR_CS_N                      (DDR_CS_N),
      .DDR_DQ                        (DDR_DQ),
      .DDR_DQS                       (DDR_DQS),
      .DDR_DM                        (DDR_DM),
         .APP_MASK_DATA                 (app_mask_df_data),
      
      .DDR_CK                        (DDR_CK),
      .DDR_CK_N                      (DDR_CK_N),
      .DDR_BA                        (DDR_BA),
      .DDR_A                         (DDR_A),
      .CLK_TB                        (clk_tb),
      .RESET_TB                      (reset_tb),
      .init_done                     (init_done),

      //TEST BENCH SIGNALS
      .WDF_ALMOST_FULL               (wr_df_almost_full),
      .AF_ALMOST_FULL                (af_almost_full),
      .BURST_LENGTH                  (burst_length),
      .READ_DATA_VALID               (rd_data_valid),
      .READ_DATA_FIFO_OUT            (rd_data_fifo_out),
      .APP_AF_ADDR                   (app_af_addr),
      .APP_AF_WREN                   (app_af_wren),
      .APP_WDF_DATA                  (app_wr_df_data),
      .APP_WDF_WREN                  (app_wr_df_wren)
      );

   mem_interface_top_test_bench_0 test_bench_00
     (
      .CLK                 (clk_tb),
      .RESET               (reset_tb),
      .WDF_ALMOST_FULL     (wr_df_almost_full),
      .AF_ALMOST_FULL      (af_almost_full),
      .BURST_LENGTH        (burst_length),
      .READ_DATA_VALID     (rd_data_valid),
      .READ_DATA_FIFO_OUT  (rd_data_fifo_out),
      .APP_AF_ADDR         (app_af_addr),
      .APP_AF_WREN         (app_af_wren),
      .APP_WDF_DATA        (app_wr_df_data),
      .APP_MASK_DATA       (app_mask_df_data),
      .APP_WDF_WREN        (app_wr_df_wren),
      .ERROR               (ERROR)
      );

endmodule