///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_v4_dm_iob.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Places the data mask signals into the IOBs.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module mem_interface_top_v4_dm_iob 
  (
   input        CLK90,
   input        MASK_DATA_RISE,
   input        MASK_DATA_FALL,
   output       DDR_DM
   );


   wire         vcc;
   wire         gnd;
   wire         data_mask;

   assign 	vcc        = 1'b1;
   assign 	gnd        = 1'b0;

   defparam 	oddr_dm.SRTYPE = "SYNC";
   defparam 	oddr_dm.DDR_CLK_EDGE = "SAME_EDGE";


   ODDR oddr_dm 
     (
      .Q  (data_mask),
      .C  (CLK90),
      .CE (vcc),
      .D1 (MASK_DATA_RISE),
      .D2 (MASK_DATA_FALL),
      .R  (gnd),
      .S  (gnd)
      );

   OBUF DM_OBUF
     (
      .I (data_mask),
      .O (DDR_DM)
      );


endmodule