///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_data_tap_inc.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:15 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: The tap logic for calibration of the memory data with respect
//              to FPGA clock is provided here. According to the edge detection
//              or not the taps in the IDELAY element of the Virtex4 devices
//              are either increased or decreased.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module mem_interface_top_data_tap_inc
  (
   input        CLK,
   input        RESET,
   input        VALID_DATA_TAP_COUNT,
   input [5:0]  DATA_TAP_COUNT,
   input        DQS_sel_done,

   output       DATA_DLYINC,
   output       DATA_DLYCE,
   output       DATA_DLYRST,
   output       DATA_TAP_SEL_DONE
   );


   reg          data_dlyinc_clk0;
   reg          data_dlyce_clk0;
   reg          data_dlyrst_clk0;
   reg [5:0]    data_tap_inc_counter;
   reg          data_tap_sel_clk;
   reg          data_tap_sel_r1;
   reg          DQS_sel_done_r;
   reg          VALID_DATA_TAP_COUNT_r;
   reg          rst_r;

   assign DATA_TAP_SEL_DONE = data_tap_sel_r1;
   assign DATA_DLYINC       = data_dlyinc_clk0;
   assign DATA_DLYCE        = data_dlyce_clk0;
   assign DATA_DLYRST       = data_dlyrst_clk0;

   always @( posedge CLK)
     rst_r <= RESET;

   always @ (posedge CLK) begin
      if (rst_r == 1'b1) begin
         data_tap_sel_clk  <= 1'b0;
      end
      else if (data_tap_inc_counter[5:0] == 6'b000001) begin
         data_tap_sel_clk  <= 1'b1;
      end
   end

   always @ (posedge CLK) begin
      if (rst_r == 1'b1) begin
         data_tap_sel_r1    <= 1'b0;
      end
      else begin
         data_tap_sel_r1    <= data_tap_sel_clk;
      end
   end

   always @(posedge CLK) begin
      if(rst_r == 1'b1)
        DQS_sel_done_r <= 1'b0;
      else if(DQS_sel_done == 1'b1)
        DQS_sel_done_r <= 1'b1;
   end

   always@(posedge CLK) begin
      if(rst_r == 1'b1)
        VALID_DATA_TAP_COUNT_r <= 1'b0;
      else
        VALID_DATA_TAP_COUNT_r <= VALID_DATA_TAP_COUNT;
   end

   always @ (posedge CLK) begin
      if (rst_r == 1'b1 || DQS_sel_done_r == 1'b0) begin
         data_dlyinc_clk0               <= 1'b0;
         data_dlyce_clk0                <= 1'b0;
         data_dlyrst_clk0               <= 1'b1;
         data_tap_inc_counter[5:0] <= 6'b000000;
      end
      else if (VALID_DATA_TAP_COUNT_r == 1'b1) begin
         data_dlyinc_clk0               <= 1'b0;
         data_dlyce_clk0                <= 1'b0;
         data_dlyrst_clk0               <= 1'b0;
         data_tap_inc_counter[5:0] <= DATA_TAP_COUNT[5:0];
      end
           else if (data_tap_inc_counter[5:0] != 6'b000000) begin
              data_dlyinc_clk0               <= 1'b1;
              data_dlyce_clk0                <= 1'b1;
              data_dlyrst_clk0               <= 1'b0;
              data_tap_inc_counter[5:0] <= data_tap_inc_counter[5:0] - 1'b1;
           end
      else                         // Data IDELAY no change mode
        begin
           data_dlyinc_clk0               <= 1'b0;
           data_dlyce_clk0                <= 1'b0;
           data_dlyrst_clk0               <= 1'b0;
           data_tap_inc_counter[5:0] <= 6'b000000;
        end
   end

endmodule