///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_data_write_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:15 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Splits the user data into the rise data and the fall data.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_data_write_0
  (
   input                            CLK,
   input                            CLK90,
   input                            RESET0,
   input                            RESET90,
   input [(`data_width*2)-1:0]      WDF_DATA,
   input [(`data_mask_width*2)-1:0] MASK_DATA,
   input                            dummy_write_pattern,
   input                            CTRL_WREN,
   input                            CTRL_DQS_RST,
   input                            CTRL_DQS_EN,
   output                           dqs_rst,
   output                           dqs_en,
   output                           wr_en,
   output [`data_width-1:0]         wr_data_rise,
   output [`data_width-1:0]         wr_data_fall,
   output [`data_mask_width-1:0]    mask_data_rise,
   output [`data_mask_width-1:0]    mask_data_fall
   );

   reg                              wr_en_clk270_r1;
   reg                              wr_en_clk90_r3;
   reg                              dqs_rst_r1;
   reg                              dqs_en_r1;
   reg                              dqs_en_r2;

   wire [143:0]                      patA;
   wire [143:0]                      pat5;
   wire [143:0]                      pat9;
   wire [143:0]                      pat6;

   reg                              dummy_flag;
   reg [`data_width-1 : 0]          dummy_rise_pattern;
   reg [`data_width-1 : 0]          dummy_fall_pattern;
   reg                              dummy_write_pattern_270;
   reg                              dummy_write_pattern_90;
   reg                              dummy_flag1;
   reg                              rst90_r;

   assign dqs_rst = dqs_rst_r1;
   assign dqs_en  = dqs_en_r2;
   assign wr_en   = wr_en_clk90_r3;

   assign patA = 144'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
   assign pat5 = 144'h555555555555555555555555555555555555;
   assign pat9 = 144'h999999999999999999999999999999999999;
   assign pat6 = 144'h666666666666666666666666666666666666;

   always @ (posedge CLK90)
     rst90_r <= RESET90;

   always @ (negedge CLK90) begin
     wr_en_clk270_r1  <= CTRL_WREN;
     dqs_rst_r1       <= CTRL_DQS_RST;
     dqs_en_r1        <= ~CTRL_DQS_EN;
   end

   always @ (negedge CLK) begin
     dqs_en_r2         <= dqs_en_r1;
   end

   always @ (posedge CLK90)
     wr_en_clk90_r3      <= wr_en_clk270_r1;

   always @(negedge CLK90)
     dummy_write_pattern_270 <= dummy_write_pattern;

   always @(posedge CLK90)
     dummy_write_pattern_90 <= dummy_write_pattern_270;

always@(posedge CLK90)
begin
  if(rst90_r)
    dummy_flag <= 1'b0;
  else if(dummy_write_pattern_90)
  begin
    if(dummy_flag)
      dummy_rise_pattern <= patA[`data_width-1 :0];
    else
      dummy_rise_pattern <= pat9[`data_width-1 :0];
    dummy_flag <= ~(dummy_flag);
  end
end

always@(posedge CLK90)
begin
  if(rst90_r)
    dummy_flag1 <= 1'b0;
  else if(dummy_write_pattern_90)
  begin
    if(dummy_flag1)
      dummy_fall_pattern <= pat5[`data_width-1 :0];
    else
      dummy_fall_pattern <= pat6[`data_width-1 :0];
  dummy_flag1 <= ~(dummy_flag1);
  end
end


   assign wr_data_rise =  dummy_write_pattern_90 ? dummy_rise_pattern :
                            WDF_DATA[(`data_width*2)-1:`data_width];
   assign wr_data_fall =  dummy_write_pattern_90 ? dummy_fall_pattern :
                            WDF_DATA[`data_width-1:0];


   assign mask_data_rise = (dummy_write_pattern_90 | ~(wr_en_clk90_r3)) ?
                           `data_mask_width'h0 :
                           MASK_DATA[(`data_mask_width*2)-1:`data_mask_width];
   assign mask_data_fall = (dummy_write_pattern_90 | ~(wr_en_clk90_r3)) ?
                           `data_mask_width'h0 :
                           MASK_DATA[`data_mask_width-1:0];

endmodule