///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_controller_iobs_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:15 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Puts the memory control signals like address, bank address, row
//              address strobe, column address strobe, write enable and clock
//              enable in the IOBs.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_controller_iobs_0
  (
   input[`row_address-1:0]    ctrl_ddr_address,
   input[`bank_address-1:0]   ctrl_ddr_ba,
   input                      ctrl_ddr_ras_L,
   input                      ctrl_ddr_cas_L,
   input                      ctrl_ddr_we_L,
   input [`no_of_cs-1:0]      ctrl_ddr_cs_L,
   input [`cke_width-1:0]     ctrl_ddr_cke,

   output [`row_address-1:0]  DDR_ADDRESS,
   output [`bank_address-1:0] DDR_BA,
   output                     DDR_RAS_L,
   output                     DDR_CAS_L,
   output                     DDR_WE_L,
   output  [`cke_width-1:0]   DDR_CKE,
   output  [`no_of_cs-1:0]    ddr_cs_L
   );



   OBUF r0
     (
      .I(ctrl_ddr_ras_L),
      .O(DDR_RAS_L)
      );

   OBUF r1
     (
      .I(ctrl_ddr_cas_L),
      .O(DDR_CAS_L)
      );

   OBUF r2
     (
      .I(ctrl_ddr_we_L),
      .O(DDR_WE_L)
      );


   
  OBUF OBUF_cs0
    (
        .I(ctrl_ddr_cs_L[0]),
        .O(ddr_cs_L[0])
      );




   
  OBUF OBUF_cke0
    (
        .I(ctrl_ddr_cke[0]),
        .O(DDR_CKE[0])
      );



   
  OBUF OBUF_r0
        (
            .I  (ctrl_ddr_address[0]),
            .O  (DDR_ADDRESS[0])
            );




  OBUF OBUF_r1
        (
            .I  (ctrl_ddr_address[1]),
            .O  (DDR_ADDRESS[1])
            );




  OBUF OBUF_r2
        (
            .I  (ctrl_ddr_address[2]),
            .O  (DDR_ADDRESS[2])
            );




  OBUF OBUF_r3
        (
            .I  (ctrl_ddr_address[3]),
            .O  (DDR_ADDRESS[3])
            );




  OBUF OBUF_r4
        (
            .I  (ctrl_ddr_address[4]),
            .O  (DDR_ADDRESS[4])
            );




  OBUF OBUF_r5
        (
            .I  (ctrl_ddr_address[5]),
            .O  (DDR_ADDRESS[5])
            );




  OBUF OBUF_r6
        (
            .I  (ctrl_ddr_address[6]),
            .O  (DDR_ADDRESS[6])
            );




  OBUF OBUF_r7
        (
            .I  (ctrl_ddr_address[7]),
            .O  (DDR_ADDRESS[7])
            );




  OBUF OBUF_r8
        (
            .I  (ctrl_ddr_address[8]),
            .O  (DDR_ADDRESS[8])
            );




  OBUF OBUF_r9
        (
            .I  (ctrl_ddr_address[9]),
            .O  (DDR_ADDRESS[9])
            );




  OBUF OBUF_r10
        (
            .I  (ctrl_ddr_address[10]),
            .O  (DDR_ADDRESS[10])
            );




  OBUF OBUF_r11
        (
            .I  (ctrl_ddr_address[11]),
            .O  (DDR_ADDRESS[11])
            );





   
  OBUF OBUF_b0
        (
            .I  (ctrl_ddr_ba[0]),
            .O  (DDR_BA[0])
            );



  OBUF OBUF_b1
        (
            .I  (ctrl_ddr_ba[1]),
            .O  (DDR_BA[1])
            );



endmodule