///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_iobs_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: This module instantiates all the iobs modules. It is the
//              interface between the main logic and the memory.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_iobs_0
  (
   input                           CLK,
   input                           CLK90,
   input                           RESET0,
   input                           RESET90,
   input [`ReadEnable-1:0]         dqs_idelay_inc,
   input [`ReadEnable-1:0]         dqs_idelay_ce,
   input [`ReadEnable-1:0]         dqs_idelay_rst,
   input [`ReadEnable-1:0]         data_idelay_inc,
   input [`ReadEnable-1:0]         data_idelay_ce,
   input [`ReadEnable-1:0]         data_idelay_rst,
   input                           dqs_rst,
   input                           dqs_en,
   input                           wr_en,
   input [`data_width-1:0]         wr_data_rise,
   input [`data_width-1:0]         wr_data_fall,
   input [`data_mask_width-1:0]    mask_data_rise,
   input [`data_mask_width-1:0]    mask_data_fall,
   input[`row_address-1  :0]       ctrl_ddr_address,
   input[`bank_address-1 :0]       ctrl_ddr_ba,
   input                           ctrl_ddr_ras_L,
   input                           ctrl_ddr_cas_L,
   input                           ctrl_ddr_we_L,
   input   [`no_of_cs-1:0]         ctrl_ddr_cs_L,
   input    [`cke_width-1:0]       ctrl_ddr_cke,
   inout [`data_width-1:0]         DDR_DQ,
   inout [`data_strobe_width-1:0]  DDR_DQS,
   output [`data_mask_width-1:0]   DDR_DM,
   output [`data_width-1:0]        rd_data_rise,
   output [`data_width-1:0]        rd_data_fall,
   output [`data_strobe_width-1:0] dqs_delayed,
   output [`clk_width-1:0]         DDR_CK,
   output [`clk_width-1:0]         DDR_CK_N,
   output [`row_address-1  :0]     DDR_ADDRESS,
   output [`bank_address-1 :0]     DDR_BA,
   output                          DDR_RAS_L,
   output                          DDR_CAS_L,
   output                          DDR_WE_L,
   output    [`cke_width-1:0]      DDR_CKE,
   output  [`no_of_cs-1:0]         ddr_cs_L
   );


   mem_interface_top_infrastructure_iobs_0 infrastructure_iobs_00
     (
      .CLK      (CLK),
      .DDR_CK   (DDR_CK),
      .DDR_CK_N (DDR_CK_N)
      );



   mem_interface_top_data_path_iobs_0 data_path_iobs_00
     (
      .CLK             (CLK),
      .CLK90           (CLK90),
      .RESET0          (RESET0),
      .RESET90         (RESET90),
      .dqs_idelay_inc  (dqs_idelay_inc),
      .dqs_idelay_ce   (dqs_idelay_ce),
      .dqs_idelay_rst  (dqs_idelay_rst),
      .dqs_rst         (dqs_rst),
      .dqs_en          (dqs_en),
      .dqs_delayed     (dqs_delayed),
      .data_idelay_inc (data_idelay_inc),
      .data_idelay_ce  (data_idelay_ce),
      .data_idelay_rst (data_idelay_rst),
      .wr_data_rise    (wr_data_rise),
      .wr_data_fall    (wr_data_fall),
      .wr_en           (wr_en),
      .rd_data_rise    (rd_data_rise),
      .rd_data_fall    (rd_data_fall),
      .mask_data_rise  (mask_data_rise),
      .mask_data_fall  (mask_data_fall),
      .DDR_DQ          (DDR_DQ),
      .DDR_DQS         (DDR_DQS),
      .DDR_DM          (DDR_DM)
      );

   mem_interface_top_controller_iobs_0 controller_iobs_00
     (
      .ctrl_ddr_address (ctrl_ddr_address),
      .ctrl_ddr_ba      (ctrl_ddr_ba),
      .ctrl_ddr_ras_L   (ctrl_ddr_ras_L),
      .ctrl_ddr_cas_L   (ctrl_ddr_cas_L),
      .ctrl_ddr_we_L    (ctrl_ddr_we_L),
      .ctrl_ddr_cs_L    (ctrl_ddr_cs_L),
      .ctrl_ddr_cke     (ctrl_ddr_cke),
      .DDR_ADDRESS      (DDR_ADDRESS),
      .DDR_BA           (DDR_BA),
      .DDR_RAS_L        (DDR_RAS_L),
      .DDR_CAS_L        (DDR_CAS_L),
      .DDR_WE_L         (DDR_WE_L),
      .DDR_CKE          (DDR_CKE),
      .ddr_cs_L         (ddr_cs_L)
      );

endmodule