///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_tap_ctrl.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: The tap control logic which claculates the relation between the
//              FPGA clock and the dqs from memory. It delays the dqs so as to
//              detect the edges of the dqs and then calculates the mid point
//              so that the data can be registered properly.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps


module mem_interface_top_tap_ctrl
  (
   input        CLK,
   input        RESET,
   input        RDY_STATUS,
   input        DQS,
   input        CTRL_DUMMYREAD_START,
   output       DLYINC,
   output       DLYCE,
   output       DLYRST,
   output       SEL_DONE,
   output       VALID_DATA_TAP_COUNT,
   output [5:0] DATA_TAP_COUNT
   );

   reg          prev_dqs_level;
   reg          dly_inc;
   reg          dly_ce;
   reg          dly_rst;
   reg [1:0]    transition;
   reg          first_edge;
   reg          second_edge;
   reg          second_edge_r1;
   reg          second_edge_r2;
   reg          second_edge_r3;
   reg          transition_rst;
   reg          sel_complete;
   reg [5:0]    tap_counter;
   reg [5:0]    first_edge_tap_count;
   reg [5:0]    second_edge_tap_count;
   reg [5:0]    pulse_width_tap_count ;
   reg [5:0]    data_bit_tap_count;
   reg [2:0]    state;
   reg          idelay_rst_idle;
   reg          idelay_rst_idle_r1;
   reg          idelay_rst_idle_r2;
   reg          idelay_rst_idle_r3;
   reg          idelay_rst_idle_r4;
   reg          idelay_rst_idle_r5;
   reg          idelay_rst_idle_r6;
   reg          idelay_inc_idle;
   reg          idelay_inc_idle_r1;
   reg          idelay_inc_idle_r2;
   reg          idelay_inc_idle_r3;
   reg          idelay_inc_idle_r4;
   reg          idelay_inc_idle_r5;
   reg          idelay_inc_idle_r6;
   reg          detect_edge_idle;
   reg          detect_edge_idle_r1;
   reg          detect_edge_idle_r2;
   reg          detect_edge_idle_r3;
   reg          detect_edge_idle_r4;
   reg          detect_edge_idle_r5;
   reg          detect_edge_idle_r6;
   reg [2:0]    first_edge_cnt;
   reg [3:0]    flag;
   reg [3:0]    dly_after_first_cnt;
   reg [5:0]    pulse_center_tap_count ;
   reg          valid_data_count;
   reg          rst_r;

   wire         data_count_valid;
   wire [3:0]   dly_after_first;
   wire         curr_dqs_level;
   wire         delay_sel_done;
   wire         reset_int;

   localparam   idelay_rst =  3'b000;
   localparam   idle       =  3'b001;
   localparam   idelay_inc =  3'b010;
   localparam   detect_edge=  3'b011;


   always @( posedge CLK)
     rst_r <= RESET;

   /// New calibration scheme edit begin
   /// New calibration scheme edit end

   assign       DLYINC               = dly_inc;
   assign       DLYCE                = dly_ce;
   assign       DLYRST               = dly_rst;
   assign       SEL_DONE             = sel_complete;
   assign       VALID_DATA_TAP_COUNT = valid_data_count;
   assign       DATA_TAP_COUNT[5:0]  = data_bit_tap_count[5:0];

   assign       data_count_valid     = (second_edge_r3 || (tap_counter[5:0] ==
                                                     6'b111111)) ? 1'b1 : 1'b0;
   assign       reset_int            = (~RDY_STATUS) || rst_r;

   assign       delay_sel_done = ((second_edge == 1'b1) || (tap_counter[5:0]==
                                                            6'b111111)) ? 1'b1 :
                (CTRL_DUMMYREAD_START == 1'b0) ? 1'b0 : sel_complete;

   assign       dly_after_first[3:0] = ((transition[1:0] == 2'b01) &&
                             (first_edge == 1'b0)) ? 4'b1001 :
                ((dly_after_first_cnt[3:0] != 4'b0000) && (dly_inc == 1'b1)) ?
                (dly_after_first_cnt[3:0] - 1'b1) : dly_after_first_cnt[3:0];

   assign       curr_dqs_level  = DQS;

   // Shift registers for controls
   always @ (posedge CLK) begin
      if (reset_int == 1'b1) begin
         second_edge_r1      <= 1'b0;
         second_edge_r2      <= 1'b0;
         second_edge_r3      <= 1'b0;
         idelay_rst_idle_r1  <= 1'b0;
         idelay_rst_idle_r2  <= 1'b0;
         idelay_rst_idle_r3  <= 1'b0;
         idelay_rst_idle_r4  <= 1'b0;
         idelay_rst_idle_r5  <= 1'b0;
         idelay_rst_idle_r6  <= 1'b0;
         idelay_inc_idle_r1  <= 1'b0;
         idelay_inc_idle_r2  <= 1'b0;
         idelay_inc_idle_r3  <= 1'b0;
         idelay_inc_idle_r4  <= 1'b0;
         idelay_inc_idle_r5  <= 1'b0;
         idelay_inc_idle_r6  <= 1'b0;
         detect_edge_idle_r1 <= 1'b0;
         detect_edge_idle_r2 <= 1'b0;
         detect_edge_idle_r3 <= 1'b0;
         detect_edge_idle_r4 <= 1'b0;
         detect_edge_idle_r5 <= 1'b0;
         detect_edge_idle_r6 <= 1'b0;
         valid_data_count    <= 1'b0;
      end
      else begin
         second_edge_r1      <= second_edge;
         second_edge_r2      <= second_edge_r1;
         second_edge_r3      <= second_edge_r2;
         idelay_rst_idle_r1  <= idelay_rst_idle;
         idelay_rst_idle_r2  <= idelay_rst_idle_r1;
         idelay_rst_idle_r3  <= idelay_rst_idle_r2;
         idelay_rst_idle_r4  <= idelay_rst_idle_r3;
         idelay_rst_idle_r5  <= idelay_rst_idle_r4;
         idelay_rst_idle_r6  <= idelay_rst_idle_r5;
         idelay_inc_idle_r1  <= idelay_inc_idle;
         idelay_inc_idle_r2  <= idelay_inc_idle_r1;
         idelay_inc_idle_r3  <= idelay_inc_idle_r2;
         idelay_inc_idle_r4  <= idelay_inc_idle_r3;
         idelay_inc_idle_r5  <= idelay_inc_idle_r4;
         idelay_inc_idle_r6  <= idelay_inc_idle_r5;
         detect_edge_idle_r1 <= detect_edge_idle;
         detect_edge_idle_r2 <= detect_edge_idle_r1;
         detect_edge_idle_r3 <= detect_edge_idle_r2;
         detect_edge_idle_r4 <= detect_edge_idle_r3;
         detect_edge_idle_r5 <= detect_edge_idle_r4;
         detect_edge_idle_r6 <= detect_edge_idle_r5;
         valid_data_count    <= data_count_valid;
      end
   end

   // Tap Delay Selection Complete for Data bus associated with a DQS
   always @ (posedge CLK) begin
      if (reset_int == 1'b1)
        sel_complete <= 1'b0;
      else
        sel_complete <= delay_sel_done;
   end

   // Start detection of second transition only after 10 taps from first transition
   always @ (posedge CLK) begin
      if (reset_int == 1'b1)
        dly_after_first_cnt[3:0] <= 4'b0000;
      else
        dly_after_first_cnt[3:0] <= dly_after_first[3:0];
   end

   // Tap Counter
   always @ (posedge CLK) begin
      if ((reset_int == 1'b1) || (tap_counter[5:0] == 6'b111111))
        tap_counter[5:0] <= 6'b000000;
      else if (dly_inc == 1'b1)
        tap_counter[5:0] <= tap_counter[5:0] + 1'b1;
   end


   // Tap value for Data IDELAY circuit
   always @ (posedge CLK) begin
      if (reset_int == 1'b1) begin
         first_edge_tap_count[5:0]   <= 6'b000000;
         first_edge_cnt           <= 3'b000;
      end
      else if ((transition[1:0] == 2'b01) && (first_edge == 1'b0)) begin
         first_edge_tap_count[5:0]   <= tap_counter[5:0];
         first_edge_cnt           <= 3'b110;
      end
      else if(dly_inc == 1'b1 && first_edge == 1'b1 && first_edge_cnt != 3'b000)
        first_edge_cnt <= first_edge_cnt- 1'b1;
   end

   always @ (posedge CLK) begin