?? mem_interface_top_data_path_iobs_0.txt
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: mig_v1_7 $
// \ \ Application : MIG
// / / Filename : mem_interface_top_data_path_iobs_0.v
// /___/ /\ Date Last Modified : $Date: 2007/02/15 12:06:15 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
//
// Device : Virtex-4
// Design Name : DDR SDRAM
// Description: This module instantiates data, data strobe and the data mask iobs.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"
module mem_interface_top_data_path_iobs_0
(
input CLK,
input CLK90,
input RESET0,
input RESET90,
input [`ReadEnable-1:0] dqs_idelay_inc,
input [`ReadEnable-1:0] dqs_idelay_ce,
input [`ReadEnable-1:0] dqs_idelay_rst,
input [`ReadEnable-1:0] data_idelay_inc,
input [`ReadEnable-1:0] data_idelay_ce,
input [`ReadEnable-1:0] data_idelay_rst,
input dqs_rst,
input dqs_en,
output [`data_strobe_width-1:0] dqs_delayed,
input [`data_width-1:0] wr_data_rise,
input [`data_width-1:0] wr_data_fall,
input wr_en,
output[`data_width-1:0] rd_data_rise,
output[`data_width-1:0] rd_data_fall,
input [`data_mask_width-1:0] mask_data_rise,
input [`data_mask_width-1:0] mask_data_fall,
inout [`data_width-1:0] DDR_DQ,
inout [`data_strobe_width-1:0] DDR_DQS,
output [`data_mask_width-1:0] DDR_DM
);
/////////////////////////////////////////////////////////////////////////////
// DQS instances
/////////////////////////////////////////////////////////////////////////////
mem_interface_top_v4_dqs_iob v4_dqs_iob0
(
.CLK (CLK),
.DLYINC (dqs_idelay_inc[0]),
.DLYCE (dqs_idelay_ce[0]),
.DLYRST (dqs_idelay_rst[0]),
.CTRL_DQS_RST (dqs_rst),
.CTRL_DQS_EN (dqs_en),
.DDR_DQS (DDR_DQS[0]),
.DQS_RISE (dqs_delayed[0])
);
mem_interface_top_v4_dqs_iob v4_dqs_iob1
(
.CLK (CLK),
.DLYINC (dqs_idelay_inc[0]),
.DLYCE (dqs_idelay_ce[0]),
.DLYRST (dqs_idelay_rst[0]),
.CTRL_DQS_RST (dqs_rst),
.CTRL_DQS_EN (dqs_en),
.DDR_DQS (DDR_DQS[1]),
.DQS_RISE (dqs_delayed[1])
);
mem_interface_top_v4_dqs_iob v4_dqs_iob2
(
.CLK (CLK),
.DLYINC (dqs_idelay_inc[0]),
.DLYCE (dqs_idelay_ce[0]),
.DLYRST (dqs_idelay_rst[0]),
.CTRL_DQS_RST (dqs_rst),
.CTRL_DQS_EN (dqs_en),
.DDR_DQS (DDR_DQS[2]),
.DQS_RISE (dqs_delayed[2])
);
mem_interface_top_v4_dqs_iob v4_dqs_iob3
(
.CLK (CLK),
.DLYINC (dqs_idelay_inc[0]),
.DLYCE (dqs_idelay_ce[0]),
.DLYRST (dqs_idelay_rst[0]),
.CTRL_DQS_RST (dqs_rst),
.CTRL_DQS_EN (dqs_en),
.DDR_DQS (DDR_DQS[3]),
.DQS_RISE (dqs_delayed[3])
);
mem_interface_top_v4_dqs_iob v4_dqs_iob4
(
.CLK (CLK),
.DLYINC (dqs_idelay_inc[1]),
.DLYCE (dqs_idelay_ce[1]),
.DLYRST (dqs_idelay_rst[1]),
.CTRL_DQS_RST (dqs_rst),
.CTRL_DQS_EN (dqs_en),
.DDR_DQS (DDR_DQS[4]),
.DQS_RISE (dqs_delayed[4])
);
mem_interface_top_v4_dqs_iob v4_dqs_iob5
(
.CLK (CLK),
.DLYINC (dqs_idelay_inc[1]),
.DLYCE (dqs_idelay_ce[1]),
.DLYRST (dqs_idelay_rst[1]),
.CTRL_DQS_RST (dqs_rst),
.CTRL_DQS_EN (dqs_en),
.DDR_DQS (DDR_DQS[5]),
.DQS_RISE (dqs_delayed[5])
);
mem_interface_top_v4_dqs_iob v4_dqs_iob6
(
.CLK (CLK),
.DLYINC (dqs_idelay_inc[1]),
.DLYCE (dqs_idelay_ce[1]),
.DLYRST (dqs_idelay_rst[1]),
.CTRL_DQS_RST (dqs_rst),
.CTRL_DQS_EN (dqs_en),
.DDR_DQS (DDR_DQS[6]),
.DQS_RISE (dqs_delayed[6])
);
mem_interface_top_v4_dqs_iob v4_dqs_iob7
(
.CLK (CLK),
.DLYINC (dqs_idelay_inc[1]),
.DLYCE (dqs_idelay_ce[1]),
.DLYRST (dqs_idelay_rst[1]),
.CTRL_DQS_RST (dqs_rst),
.CTRL_DQS_EN (dqs_en),
.DDR_DQS (DDR_DQS[7]),
.DQS_RISE (dqs_delayed[7])
);
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// DM instances
/////////////////////////////////////////////////////////////////////////////
mem_interface_top_v4_dm_iob v4_dm_iob0
(
.CLK90 (CLK90),
.MASK_DATA_RISE (mask_data_rise[0]),
.MASK_DATA_FALL (mask_data_fall[0]),
.DDR_DM (DDR_DM[0])
);
mem_interface_top_v4_dm_iob v4_dm_iob1
(
.CLK90 (CLK90),
.MASK_DATA_RISE (mask_data_rise[1]),
.MASK_DATA_FALL (mask_data_fall[1]),
.DDR_DM (DDR_DM[1])
);
mem_interface_top_v4_dm_iob v4_dm_iob2
(
.CLK90 (CLK90),
.MASK_DATA_RISE (mask_data_rise[2]),
.MASK_DATA_FALL (mask_data_fall[2]),
.DDR_DM (DDR_DM[2])
);
mem_interface_top_v4_dm_iob v4_dm_iob3
(
.CLK90 (CLK90),
.MASK_DATA_RISE (mask_data_rise[3]),
.MASK_DATA_FALL (mask_data_fall[3]),
.DDR_DM (DDR_DM[3])
);
mem_interface_top_v4_dm_iob v4_dm_iob4
(
.CLK90 (CLK90),
.MASK_DATA_RISE (mask_data_rise[4]),
.MASK_DATA_FALL (mask_data_fall[4]),
.DDR_DM (DDR_DM[4])
);
mem_interface_top_v4_dm_iob v4_dm_iob5
(
.CLK90 (CLK90),
.MASK_DATA_RISE (mask_data_rise[5]),
.MASK_DATA_FALL (mask_data_fall[5]),
.DDR_DM (DDR_DM[5])
);
mem_interface_top_v4_dm_iob v4_dm_iob6
(
.CLK90 (CLK90),
.MASK_DATA_RISE (mask_data_rise[6]),
.MASK_DATA_FALL (mask_data_fall[6]),
.DDR_DM (DDR_DM[6])
);
mem_interface_top_v4_dm_iob v4_dm_iob7
(
.CLK90 (CLK90),
.MASK_DATA_RISE (mask_data_rise[7]),
.MASK_DATA_FALL (mask_data_fall[7]),
.DDR_DM (DDR_DM[7])
);
/////////////////////////////////////////////////////////////////////////////
//DQ_IOB4 instances
/////////////////////////////////////////////////////////////////////////////
mem_interface_top_v4_dq_iob v4_dq_iob0
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[0]),
.WRITE_DATA_FALL (wr_data_fall[0]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[0]),
.READ_DATA_RISE (rd_data_rise[0]),
.READ_DATA_FALL (rd_data_fall[0])
);
mem_interface_top_v4_dq_iob v4_dq_iob1
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[1]),
.WRITE_DATA_FALL (wr_data_fall[1]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[1]),
.READ_DATA_RISE (rd_data_rise[1]),
.READ_DATA_FALL (rd_data_fall[1])
);
mem_interface_top_v4_dq_iob v4_dq_iob2
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[2]),
.WRITE_DATA_FALL (wr_data_fall[2]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[2]),
.READ_DATA_RISE (rd_data_rise[2]),
.READ_DATA_FALL (rd_data_fall[2])
);
mem_interface_top_v4_dq_iob v4_dq_iob3
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[3]),
.WRITE_DATA_FALL (wr_data_fall[3]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[3]),
.READ_DATA_RISE (rd_data_rise[3]),
.READ_DATA_FALL (rd_data_fall[3])
);
mem_interface_top_v4_dq_iob v4_dq_iob4
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[4]),
.WRITE_DATA_FALL (wr_data_fall[4]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[4]),
.READ_DATA_RISE (rd_data_rise[4]),
.READ_DATA_FALL (rd_data_fall[4])
);
mem_interface_top_v4_dq_iob v4_dq_iob5
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
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