?? mem_interface_top_data_path_iobs_0.txt
字號(hào):
.READ_DATA_RISE (rd_data_rise[44]),
.READ_DATA_FALL (rd_data_fall[44])
);
mem_interface_top_v4_dq_iob v4_dq_iob45
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[45]),
.WRITE_DATA_FALL (wr_data_fall[45]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[45]),
.READ_DATA_RISE (rd_data_rise[45]),
.READ_DATA_FALL (rd_data_fall[45])
);
mem_interface_top_v4_dq_iob v4_dq_iob46
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[46]),
.WRITE_DATA_FALL (wr_data_fall[46]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[46]),
.READ_DATA_RISE (rd_data_rise[46]),
.READ_DATA_FALL (rd_data_fall[46])
);
mem_interface_top_v4_dq_iob v4_dq_iob47
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[47]),
.WRITE_DATA_FALL (wr_data_fall[47]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[47]),
.READ_DATA_RISE (rd_data_rise[47]),
.READ_DATA_FALL (rd_data_fall[47])
);
mem_interface_top_v4_dq_iob v4_dq_iob48
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[48]),
.WRITE_DATA_FALL (wr_data_fall[48]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[48]),
.READ_DATA_RISE (rd_data_rise[48]),
.READ_DATA_FALL (rd_data_fall[48])
);
mem_interface_top_v4_dq_iob v4_dq_iob49
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[49]),
.WRITE_DATA_FALL (wr_data_fall[49]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[49]),
.READ_DATA_RISE (rd_data_rise[49]),
.READ_DATA_FALL (rd_data_fall[49])
);
mem_interface_top_v4_dq_iob v4_dq_iob50
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[50]),
.WRITE_DATA_FALL (wr_data_fall[50]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[50]),
.READ_DATA_RISE (rd_data_rise[50]),
.READ_DATA_FALL (rd_data_fall[50])
);
mem_interface_top_v4_dq_iob v4_dq_iob51
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[51]),
.WRITE_DATA_FALL (wr_data_fall[51]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[51]),
.READ_DATA_RISE (rd_data_rise[51]),
.READ_DATA_FALL (rd_data_fall[51])
);
mem_interface_top_v4_dq_iob v4_dq_iob52
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[52]),
.WRITE_DATA_FALL (wr_data_fall[52]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[52]),
.READ_DATA_RISE (rd_data_rise[52]),
.READ_DATA_FALL (rd_data_fall[52])
);
mem_interface_top_v4_dq_iob v4_dq_iob53
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[53]),
.WRITE_DATA_FALL (wr_data_fall[53]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[53]),
.READ_DATA_RISE (rd_data_rise[53]),
.READ_DATA_FALL (rd_data_fall[53])
);
mem_interface_top_v4_dq_iob v4_dq_iob54
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[54]),
.WRITE_DATA_FALL (wr_data_fall[54]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[54]),
.READ_DATA_RISE (rd_data_rise[54]),
.READ_DATA_FALL (rd_data_fall[54])
);
mem_interface_top_v4_dq_iob v4_dq_iob55
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[55]),
.WRITE_DATA_FALL (wr_data_fall[55]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[55]),
.READ_DATA_RISE (rd_data_rise[55]),
.READ_DATA_FALL (rd_data_fall[55])
);
mem_interface_top_v4_dq_iob v4_dq_iob56
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[56]),
.WRITE_DATA_FALL (wr_data_fall[56]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[56]),
.READ_DATA_RISE (rd_data_rise[56]),
.READ_DATA_FALL (rd_data_fall[56])
);
mem_interface_top_v4_dq_iob v4_dq_iob57
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[57]),
.WRITE_DATA_FALL (wr_data_fall[57]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[57]),
.READ_DATA_RISE (rd_data_rise[57]),
.READ_DATA_FALL (rd_data_fall[57])
);
mem_interface_top_v4_dq_iob v4_dq_iob58
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[58]),
.WRITE_DATA_FALL (wr_data_fall[58]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[58]),
.READ_DATA_RISE (rd_data_rise[58]),
.READ_DATA_FALL (rd_data_fall[58])
);
mem_interface_top_v4_dq_iob v4_dq_iob59
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[59]),
.WRITE_DATA_FALL (wr_data_fall[59]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[59]),
.READ_DATA_RISE (rd_data_rise[59]),
.READ_DATA_FALL (rd_data_fall[59])
);
mem_interface_top_v4_dq_iob v4_dq_iob60
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[60]),
.WRITE_DATA_FALL (wr_data_fall[60]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[60]),
.READ_DATA_RISE (rd_data_rise[60]),
.READ_DATA_FALL (rd_data_fall[60])
);
mem_interface_top_v4_dq_iob v4_dq_iob61
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[61]),
.WRITE_DATA_FALL (wr_data_fall[61]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[61]),
.READ_DATA_RISE (rd_data_rise[61]),
.READ_DATA_FALL (rd_data_fall[61])
);
mem_interface_top_v4_dq_iob v4_dq_iob62
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[62]),
.WRITE_DATA_FALL (wr_data_fall[62]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[62]),
.READ_DATA_RISE (rd_data_rise[62]),
.READ_DATA_FALL (rd_data_fall[62])
);
mem_interface_top_v4_dq_iob v4_dq_iob63
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[1]),
.DATA_DLYCE (data_idelay_ce[1]),
.DATA_DLYRST (data_idelay_rst[1]),
.WRITE_DATA_RISE (wr_data_rise[63]),
.WRITE_DATA_FALL (wr_data_fall[63]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[63]),
.READ_DATA_RISE (rd_data_rise[63]),
.READ_DATA_FALL (rd_data_fall[63])
);
endmodule
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