///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_wr_data_fifo_16.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Instantiates the block RAM based FIFO to store the user interface
//              data into it and read after a specified amount in already 
//              written. The reading starts when the almost full signal is 
//              generated whose offset is programmable.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module mem_interface_top_wr_data_fifo_16
  (
   input         clk0,
   input         clk90,
   input         rst,
   input [31:0]  app_Wdf_data,
   input [3:0]   app_mask_data,
   input         app_Wdf_WrEn,
   input         ctrl_Wdf_RdEn,
   output [31:0] Wdf_data,
   output [3:0]  mask_data,
   output        wr_df_almost_full
   );


   reg ctrl_Wdf_RdEn_270;
   reg ctrl_Wdf_RdEn_90;
   reg rst_r;

   always @( posedge clk0 )
     rst_r <= rst;

   always @(negedge clk90)
     ctrl_Wdf_RdEn_270 <= ctrl_Wdf_RdEn;


   always @(posedge clk90)
     ctrl_Wdf_RdEn_90 <= ctrl_Wdf_RdEn_270;

   defparam Wdf_1.ALMOST_FULL_OFFSET = 12'h00F;
   defparam Wdf_1.ALMOST_EMPTY_OFFSET = 12'h007;
   defparam Wdf_1.DATA_WIDTH = 36;
   defparam Wdf_1.FIRST_WORD_FALL_THROUGH = "FALSE";

   FIFO16  Wdf_1
     (
      .ALMOSTEMPTY (),
      .ALMOSTFULL  (wr_df_almost_full),
      .DO          (Wdf_data[31:0]),
      .DOP         (mask_data[3:0]),
      .EMPTY       (),
      .FULL        (),
      .RDCOUNT     (),
      .RDERR       (),
      .WRCOUNT     (),
      .WRERR       (),
      .DI          (app_Wdf_data[31:0]),
      .DIP         (app_mask_data[3:0]),
      .RDCLK       (clk90),
      .RDEN        (ctrl_Wdf_RdEn_90),
      .RST         (rst_r),
      .WRCLK       (clk0),
      .WREN        (app_Wdf_WrEn)
      );


endmodule