###################### clock constraints ########################specifying clock periods#133 MHzNET "sys_clk"     	PERIOD = 7.5ns ;NET "fpga_clk"     	PERIOD = 7.5ns ;NET "fpga_clk2x" 	PERIOD = 3.76ns;NET fpga_clk 	 TNM=c1x;NET fpga_clk2x   TNM=c2x;TIMESPEC TS10= FROM: c1x: TO: c2x: 3.76ns;TIMESPEC TS11= FROM: c2x: TO: c1x: 3.76ns;#the first f/fs for lac_clk and lac_clk90 are not covered by the clock timespec#their inputs comes straight from sys_clk, so it's neccessary to have separate constraint for those paths. #NET I_ddr_ctlr/clk_dlls/sys_clk_dly MAXDELAY = 0.4ns;#NET I_ddr_ctlr/clk_dlls/fpga_lac_clk_out MAXDELAY = 2.5ns;################################# input and output constraints ###################################The min setup (Tis) of the SDRAM-75 is 0.9ns, plus 500ps of clk jitter & board delay#we need to add this OFFSET to all outputs to SDRAM#NET ddr_ad<*> OFFSET = OUT : 1.4 : BEFORE : sys_clk ;NET ddr_rasb  OFFSET = OUT : 1.4 : BEFORE : sys_clk ;NET ddr_casb  OFFSET = OUT : 1.4 : BEFORE : sys_clk ;NET ddr_web   OFFSET = OUT : 1.4 : BEFORE : sys_clk ;NET ddr_ba<*> OFFSET = OUT : 1.4 : BEFORE : sys_clk ;##The max clock-to-out (Tac) of the DDR SDRAM-75 is .75ns, plus 1ns of clk jitter & board delay#we need to add this OFFSET to all inputs from SDRAM#NET ddr_dq<*> OFFSET = IN : 1.8 : AFTER : sys_clk;############################################ set NODELAY attribute for input signals ############################################By default, the IBUF has a DELAY element to guarantee 0 hold time#By turning off the DELAY element, we save ~2ns in IBUF delayNET ddr_dq<*> NODELAY;NET sys_cmd<*> NODELAY;NET sys_addr<*> NODELAY;NET sys_data_i<*> NODELAY;#Set FAST attribute for all outputs
NET ddr_ad<*> FAST;
NET ddr_rasb FAST;
NET ddr_casb FAST;
NET ddr_web FAST;
NET ddr_ba<*> FAST;
NET ddr_dm<*> FAST;
NET ddr_dq<*> FAST;
NET ddr_clk FAST;
NET ddr_clkb FAST;
NET ddr_dqs<*> FAST;
NET ddr_csb FAST;
NET ddr_cke FAST;
NET sys_data_o<*> FAST;
NET sys_ref_ack FAST;
NET sys_data_valid FAST;

#Set IOSTANDARD as SSTL2_II_DCI for all IOs
# outputs   
 NET ddr_ad<*> IOSTANDARD = SSTL2_II_DCI; 
 NET ddr_dm<*> IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_ba<*> IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_rasb IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_casb IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_web IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_clk IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_clkb IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_dqs<*> IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_csb IOSTANDARD = SSTL2_II_DCI;  
 NET ddr_cke IOSTANDARD = SSTL2_II_DCI;  
 NET sys_data_o<*> IOSTANDARD = SSTL2_II_DCI;  
 NET sys_ref_ack IOSTANDARD = SSTL2_II_DCI;  
 NET sys_data_valid IOSTANDARD = SSTL2_II_DCI;  
   # Inouts
 NET ddr_dq<*> IOSTANDARD = SSTL2_II_DCI;  
  # Inputs
 NET sys_addr<*> IOSTANDARD = SSTL2_II_DCI;  
 NET sys_data_i<*> IOSTANDARD = SSTL2_II_DCI; 
 NET sys_cmd<*> IOSTANDARD = SSTL2_II_DCI; 
 NET sys_reset_n IOSTANDARD = SSTL2_II_DCI;  
 NET sys_clk IOSTANDARD = SSTL2_II_DCI;  
 NET sys_clk_fb IOSTANDARD = SSTL2_II_DCI;