-- $Id: clock_module_ref.vhd,v 1.1 2003/06/26 13:37:25 anitas Exp $-- clock_module_ref.vhd----  ***************************************************************************--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **--  **                                                                       **--  **  This text contains proprietary, confidential                         **--  **  information of Xilinx, Inc. , is distributed by                      **--  **  under license from Xilinx, Inc., and may be used,                    **--  **  copied and/or disclosed only pursuant to the terms                   **--  **  of a valid license agreement with Xilinx, Inc.                       **--  **                                                                       **--  **  Unmodified source code is guaranteed to place and route,             **--  **  function and run at speed according to the datasheet                 **--  **  specification. Source code is provided "as-is", with no              **--  **  obligation on the part of Xilinx to provide support.                 **--  **                                                                       **--  **  Xilinx Hotline support of source code IP shall only include          **--  **  standard level Xilinx Hotline support, and will only address         **--  **  issues and questions related to the standard released Netlist        **--  **  version of the core (and thus indirectly, the original core source). **--  **                                                                       **--  **  The Xilinx Support Hotline does not have access to source            **--  **  code and therefore cannot answer specific questions related          **--  **  to source HDL. The Xilinx Support Hotline will only be able          **--  **  to confirm the problem in the Netlist version of the core.           **--  **                                                                       **--  **  This copyright and support notice must be retained as part           **--  **  of this text at all times.                                           **--  ***************************************************************************--------------------------------------------------------------------------------- Filename:        clock_module_ref.vhd-- Version:         v1.00a-- Description:     This is a DCM that takes an input clock (ref_clk) and --                  increases it (by CLKFX_MULTIPLY/CLKFX_DIVIDE) to produce  --                  the CLK_FX_OUT output clock. It also provides a divisor --                  function to produce the CLK_DV_OUT output clock.--                  Only connect the output clocks required by your application.----------------------------------------------------------------------------------- Structure: ----                  clock_module_ref.vhd----------------------------------------------------------------------------------- Author:      ALS-- History:--  ALS         06-17-2003      -- First version---------------------------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;library UNISIM;use UNISIM.vcomponents.all;--------------------------------------------------------------------------------- Port Declaration---------------------------------------------------------------------------------------------------------------------------------------------------------------- Definition of Ports:----      Ref_clk         -- input reference clock--      Clkdv_out       -- divided output clock --      Clkfx_out       -- mult/div output clock--      Sys_rst_n       -- input reset signal--      Sys_rst         -- output reset signal (input signal inverted)---------------------------------------------------------------------------------------------------------------------------------------------------------------- Entity Section-------------------------------------------------------------------------------entity clock_module_ref is    port (        Ref_clk     : in std_logic;      -- input reference clock        Sys_rst_n   : in std_logic;      -- input reset signal        Clkdv_out   : out std_logic;     -- divided clock output        Clkfx_out   : out std_logic;     -- freq synthesizer clock output        Sys_rst     : out std_logic);    -- output reset signalend clock_module_ref;--------------------------------------------------------------------------------- Architecture Section-------------------------------------------------------------------------------architecture struct of clock_module_ref is--------------------------------------------------------------------------------- Signal  Declarations-------------------------------------------------------------------------------signal clkfb_in         : std_logic;signal clkdv_buf        : std_logic;signal clkfx_buf        : std_logic;signal clk0_buf         : std_logic;signal gnd              : std_logic;signal not_sys_rst_n    : std_logic;signal dcmlocked        : std_logic;--------------------------------------------------------------------------------- DCM attributes--------------------------------------------------------------------------------- CLK_FX_OUT is 13/8 of ref clock-- CLK_DV_OUT is 1/2 of ref clock-- Change generics for simulation-- Change attributes for implementationattribute CLK_FEEDBACK                  : string;attribute CLK_FEEDBACK of DCM_INST      : label is "1X";attribute CLKDV_DIVIDE                  : real;attribute CLKDV_DIVIDE of DCM_INST      : label is 2.0;attribute CLKFX_DIVIDE                  : integer;attribute CLKFX_DIVIDE of DCM_INST      : label is 8;attribute CLKFX_MULTIPLY                : integer;attribute CLKFX_MULTIPLY of DCM_INST    : label is 13;attribute CLKIN_DIVIDE_BY_2             : boolean;attribute CLKIN_DIVIDE_BY_2 of DCM_INST : label is FALSE;attribute CLKIN_PERIOD                  : real;attribute CLKIN_PERIOD of DCM_INST      : label is 20.0;attribute CLKOUT_PHASE_SHIFT            : string;attribute CLKOUT_PHASE_SHIFT of DCM_INST : label is "NONE";attribute DESKEW_ADJUST                 : string;attribute DESKEW_ADJUST of DCM_INST     : label is "SYSTEM_SYNCHRONOUS";attribute DFS_FREQUENCY_MODE            : string;attribute DFS_FREQUENCY_MODE of DCM_INST : label is "LOW";attribute DLL_FREQUENCY_MODE            : string;attribute DLL_FREQUENCY_MODE of DCM_INST : label is "LOW";attribute DUTY_CYCLE_CORRECTION         : boolean;attribute DUTY_CYCLE_CORRECTION of DCM_INST : label is TRUE;attribute PHASE_SHIFT                   : integer;attribute PHASE_SHIFT of DCM_INST       : label is 0;attribute STARTUP_WAIT                  : boolean;attribute STARTUP_WAIT of DCM_INST      : label is FALSE;--------------------------------------------------------------------------------- Component Declarations-------------------------------------------------------------------------------component DCM generic(     DFS_FREQUENCY_MODE : string := "LOW";    DLL_FREQUENCY_MODE : string := "LOW";    DUTY_CYCLE_CORRECTION : boolean := TRUE;    CLKIN_DIVIDE_BY_2 : boolean := FALSE;    CLK_FEEDBACK : string := "1X";    CLKOUT_PHASE_SHIFT : string := "NONE";    DSS_MODE : string := "NONE";    FACTORY_JF : bit_vector := X"C080";    STARTUP_WAIT : boolean := false;    PHASE_SHIFT : integer := 0;    CLKFX_MULTIPLY : integer := 13;    CLKFX_DIVIDE : integer := 8;    CLKDV_DIVIDE : real := 2.0;    CLKIN_PERIOD : real := 20.0;    DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"  );    port (    CLKIN : in std_logic;    CLKFB : in std_logic;    RST : in std_logic;    PSEN : in std_logic;    PSINCDEC : in std_logic;    PSCLK : in std_logic;    DSSEN : in std_logic;    CLK0 : out std_logic;    CLK90 : out std_logic;    CLK180 : out std_logic;    CLK270 : out std_logic;    CLKDV : out std_logic;    CLK2X : out std_logic;    CLK2X180 : out std_logic;    CLKFX : out std_logic;    CLKFX180 : out std_logic;    STATUS : out std_logic_vector (7 downto 0);    LOCKED : out std_logic;    PSDONE : out std_logic    );end component;component BUFG  port (    I : in std_logic;    O : out std_logic    );end component;------------------------------------------------------------------------------begin------------------------------------------------------------------------------    -- set ground    gnd <= '0';    -- determine resets    not_sys_rst_n    <= not sys_rst_n;    sys_rst          <= not_sys_rst_n when dcmlocked ='1' else '1';-- Instantiate the DCM-- CLK_FX_OUT is 13/8 of ref clock-- CLK_DV_OUT is 1/2 of ref clock-- Change generics for simulation-- Change attributes for implementation   DCM_INST : DCM    Generic map (      CLK_FEEDBACK => "1X",      CLKDV_DIVIDE => 2.0,      CLKFX_DIVIDE => 8,      CLKFX_MULTIPLY => 13,      CLKIN_DIVIDE_BY_2 => FALSE,      CLKIN_PERIOD => 20.0,      CLKOUT_PHASE_SHIFT => "NONE",      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",      DFS_FREQUENCY_MODE => "LOW",      DLL_FREQUENCY_MODE => "LOW",      DUTY_CYCLE_CORRECTION => TRUE,      PHASE_SHIFT => 0,      STARTUP_WAIT => FALSE)     port map (      CLKIN     => Ref_clk,      CLKFB     => clkfb_in,      RST       => not_sys_rst_n,      PSEN      => gnd,      PSINCDEC  => gnd,      PSCLK     => gnd,      DSSEN     => gnd,      CLK0      => clk0_buf,      LOCKED    => dcmlocked,      CLKDV     => clkdv_buf,      CLKFX     => clkfx_buf);---- CLK0 Global Buffer--   CLK0_BUFG_INST : BUFG     port map (      I => clk0_buf,      O => clkfb_in);---- CLKDV Global Buffer--   CLKDV_BUFG_INST : BUFG     port map (      I => clkdv_buf,      O => Clkdv_out);---- CLKFX Global Buffer--   CLKFX_BUFG_INST : BUFG     port map (      I => clkfx_buf,      O => Clkfx_out);end struct;