library IEEE;
use IEEE.std_logic_1164.all;

------------- for debug --------------
--use WORK.sd_rd_state.all;
--use WORK.sd_wr_state.all;
--------------------------------------

entity sd_reader is
	port
	(
		clk:			in std_logic;	-- from bus
		clk_sd:			in std_logic;	-- sd card clk
		reset:			in std_logic;	-- from bus
		chipselect:		in std_logic;	-- from bus
		address:		in std_logic_vector( 1 downto 0 ); -- from bus
		write:			in std_logic;	-- from bus
		read:			in std_logic;	-- from bus
		writedata:		in std_logic_vector( 15 downto 0 ); -- from bus
		sd_cmd:			inout std_logic; -- export sd cmt
		sd_data:		inout std_logic_vector( 3 downto 0 ); -- export sd data
		waitrequest:	out std_logic;	-- to bus
------------- for debug --------------
--		owr_stat:		out SD_WR_STAT;
--		ord_stat:		out SD_RD_STAT;
--		owr_buzy:		out std_logic;
--		oreadm:			out std_logic;
--------------------------------------
		readdata:		out std_logic_vector( 15 downto 0 ) -- to bus
	);
end sd_reader;

architecture RTL of sd_reader is
	
	constant BLOCK_LEN_LOG2:	integer := 9;
	constant FIFO_DEPTH_LOG2:	integer := 11;
	
	component sd_rd
		generic
		(
			BLOCK_LEN_LOG2:	integer
		);
		port
		(
			clk:			in std_logic;	-- from bus
			reset:			in std_logic;	-- from bus
			chipselect:		in std_logic;	-- from bus
			address:		in std_logic_vector( 1 downto 0 ); -- from bus
			write:			in std_logic;	-- from bus
			read:			in std_logic;	-- from bus
			writedata:		in std_logic_vector( 15 downto 0 ); -- from bus
			wr_buzy:		in std_logic;	-- from sd_wr (async)
			cardready:		in std_logic;	-- from sd_wr (async)
			crcerr:			in std_logic;	-- from recvdata (async)
			rdempty:		in std_logic;	-- from dcfifo
			rdusedw: 		in std_logic_vector( 10 downto 0 ); -- from dcfifo
			data:			in std_logic_vector( 15 downto 0 ); -- from dcfifo
			waitrequest:	out std_logic;	-- to bus
			readdata:		out std_logic_vector( 15 downto 0 ); -- to bus
			wr_init:		out std_logic;	-- to sd_wr (async)
			wr_read:		out std_logic;	-- to sd_wr (async)
			wr_readm:		out std_logic;	-- to sd_wr (async)
			dataaddr:		out std_logic_vector( 31 downto 0 ); -- to sd_wr (async)
			autoreread:		out std_logic;	-- to sd_wr (async)
			rdreq:			out std_logic;	-- to dcfifo
------------- for debug ---------------
--			ostat:			out SD_RD_STAT;
--			owr_buzy_r:		out std_logic;
--			owr_buzy_dl:	out std_logic;
---------------------------------------
			areset:			out std_logic	-- to dcfifo, sd_wr, sendcmd, recvresp, recvdata
		);
	end component;
	
	component sd_wr
		generic
		(
			BLOCK_LEN_LOG2:	integer;
			FIFO_DEPTH_LOG2:integer
		);
		port
		(
			clk:			in std_logic;	-- sd clk
			areset:			in std_logic;	-- async reset
			init:			in std_logic;	-- from sd_rd (async)
			read:			in std_logic;	-- from sd_rd (async)
			readm:			in std_logic;	-- from sd_rd (async)
			dataaddr:		in std_logic_vector( 31 downto 0 ); -- from sd_rd (async)
			autoreread:		in std_logic;	-- from sd_rd (async)
			sc_buzy:		in std_logic;	-- from sendcmd
			sc_q:			in std_logic;	-- from sendcmd
			rr_buzy:		in std_logic;	-- from recvresp
			rr_content:		in std_logic_vector( 126 downto 0 ); -- from recvresp
			rr_crcerr:		in std_logic;	-- from recvresp
			rd_buzy:		in std_logic;	-- from recvdata
			rd_crcerr:		in std_logic;	-- from recvdata
			wrusedw:		in std_logic_vector( 11 downto 0 ); -- from dcfifo
			sd_cmd:			inout std_logic; -- sd cmt
			sd_data:		inout std_logic_vector( 3 downto 0 ); -- sd data
			buzy:			out std_logic;	-- to sd_rd (async)
			cardready:		out std_logic;	-- to sd_rd (async)
			sc_send:		out std_logic;	-- to sendcmd
			sc_cmdno:		out std_logic_vector( 5 downto 0 ); -- to sendcmd
			sc_content:		out std_logic_vector( 31 downto 0 ); -- to sendcmd
			rr_recv:		out std_logic;	-- to recvresp
			rr_longresp:	out std_logic;	-- to recvresp
			rr_cmd:			out std_logic;	-- to recvresp
			rd_recv:		out std_logic;	-- to recvdata
			rd_data:		out std_logic_vector( 3 downto 0 );	-- to recvdata
--------------- for debug ---------------------
--			ostat:			out SD_WR_STAT;
-----------------------------------------------
			aclr:			out std_logic	-- to dcfifo
		);
	end component;
	
	component sendcmd
		port
		(
			clk:		in std_logic;	-- sd clk
			areset:		in std_logic;	-- async reset
			send:		in std_logic;	-- send request
			cmdno:		in std_logic_vector( 5 downto 0 ); -- cmd number
			content:	in std_logic_vector( 31 downto 0 ); -- cmd content
			buzy:		out std_logic;	-- buzy sending
-------- for debug ---------------
--			ocnt:		out integer range 0 to 39;
--			ocmd:		out std_logic_vector( 39 downto 0 );
--			ocrc:		out std_logic_vector( 6 downto 0 );
------------------------------------
			q:			out std_logic	-- to sd cmd
		);
	end component;
	
	component recvresp
		port
		(
			clk:		in std_logic;	-- sd clk
			areset:		in std_logic;	-- async reset
			recv:		in std_logic;	-- recv response
			longresp:	in std_logic;	-- long response(136) /short(48)
			cmd:		in std_logic;	-- cmd port
			buzy:		out std_logic;	-- buzy receiving
			content:	out std_logic_vector( 126 downto 0 ); -- response content
	---------- for debug ----------------
	--		ocnt:		out integer range 0 to 126;
	--		ocrc:		out std_logic_vector( 6 downto 0 );
	-------------------------------------
			crcerr:		out std_logic	-- response crc error
		);
	end component;
	
	component recvdata 
		generic
		(
			BLOCK_LEN_LOG2:	integer
		);
		port
		(
			clk:		in std_logic;
			areset:		in std_logic;	-- async reset
			recv:		in std_logic;	-- from sd_wr
			data:		in std_logic_vector( 3 downto 0 ); -- sd_data
			buzy:		out std_logic;	-- buzy receiving
			crcerr:		out std_logic;	-- data crc error (async)
			wrreq:		out std_logic;	-- to dcfifo
------------- for debug -------------------
--			obitcnt:	out integer range 0 to 7;
--			ocnt:		out integer range 0 to 4095;
--			ocrc:		out std_logic_vector( 15 downto 0 );
-------------------------------------------
			q:			out std_logic_vector( 7 downto 0 ) -- to dcfifo
		);
	end component;
	
	component dcfifo_sd
		PORT
		(
			aclr		: IN STD_LOGIC ;
			data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			rdclk		: IN STD_LOGIC ;
			rdreq		: IN STD_LOGIC ;
			wrclk		: IN STD_LOGIC ;
			wrreq		: IN STD_LOGIC ;
			q			: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
			rdempty		: OUT STD_LOGIC ;
			rdusedw		: OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
			wrusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
		);
	end component;
	
	signal t_wr_buzy:		std_logic;	-- sd_wr to sd_rd
	signal t_cardready:		std_logic;	-- sd_wr to sd_rd
	signal t_rd_crcerr:		std_logic;	-- recvdata to sd_rd
	signal t_rdempty:		std_logic;	-- dcfifo to sd_rd
	signal t_fifo_data:		std_logic_vector( 15 downto 0 ); -- dcfifo to sd_rd
	signal t_wr_init:		std_logic;	-- sd_rd to sd_wr
	signal t_wr_read:		std_logic;	-- sd_rd to sd_wr
	signal t_dataaddr:		std_logic_vector( 31 downto 0 ); -- sd_rd to sd_wr
	signal t_rdreq:			std_logic;	-- sd_rd to dcfifo
	signal t_areset:		std_logic;	-- sd_rd to sd_wr, sendcmd, recvresp, recvdata, dcfifo
	signal t_sc_buzy:		std_logic;	-- sendcmd to sd_wr
	signal t_sc_q:			std_logic;	-- sendcmd to sd_wr
	signal t_rr_buzy:		std_logic;	-- recvresp to sd_wr
	signal t_rr_content:	std_logic_vector( 126 downto 0 ); -- recvresp to sd_wr
	signal t_rr_crcerr:		std_logic;	-- recvresp to sd_wr
	signal t_rd_buzy:		std_logic;	-- recvdata to sd_wr
	signal t_sc_send:		std_logic;	-- sd_wr to sendcmd
	signal t_sc_cmdno:		std_logic_vector( 5 downto 0 ); -- sd_wr to sendcmd
	signal t_sc_content:	std_logic_vector( 31 downto 0 ); -- sd_wr to sendcmd
	signal t_rr_recv:		std_logic;	-- sd_wr to recvresp
	signal t_rr_longresp:	std_logic;	-- sd_wr to recvresp
	signal t_rr_cmd:		std_logic;	-- sd_wr to recvresp
	signal t_rd_recv:		std_logic;	-- sd_wr to recvdata
	signal t_rd_data:		std_logic_vector( 3 downto 0 ); -- sd_wr to recvdata
	signal t_wrreq:			std_logic;	-- recvdata to dcfifo
	signal t_rd_q:			std_logic_vector( 7 downto 0 );	-- recvdata to dcfifo
	signal t_autoreread:	std_logic;	-- sd_rd to sd_wr
	signal t_aclr:			std_logic;	-- sd_wr to dcfifo
	signal t_rdusedw:		std_logic_vector( 10 downto 0 ); -- dcfifo to sd_rd
	signal t_wr_readm:		std_logic;	-- sd_rd to sd_wr
	signal t_wrusedw:		std_logic_vector( 11 downto 0 ); -- dcfifo to sd_wr
	
begin
	
	Sd_rd_inst: sd_rd
		generic map
		(
			BLOCK_LEN_LOG2	=>	BLOCK_LEN_LOG2
		)
		port map
		(
			clk				=>	clk,
			reset			=>	reset,
			chipselect		=>	chipselect,
			address			=>	address,
			write			=>	write,
			read			=>	read,
			writedata		=>	writedata,
			wr_buzy			=>	t_wr_buzy,
			cardready		=>	t_cardready,
			crcerr			=>	t_rd_crcerr,
			rdempty			=>	t_rdempty,
			rdusedw 		=>	t_rdusedw,
			data			=>	t_fifo_data,
			waitrequest		=>	waitrequest,
			readdata		=>	readdata,
			wr_init			=>	t_wr_init,
			wr_read			=>	t_wr_read,
			wr_readm		=>	t_wr_readm,
			dataaddr		=>	t_dataaddr,
			autoreread		=>	t_autoreread,
			rdreq			=>	t_rdreq,
------------- for debug ---------------
--			ostat			=>	ord_stat,
--			owr_buzy_r:		out std_logic;
--			owr_buzy_dl:	out std_logic;
---------------------------------------
			areset			=>	t_areset
		);
	
	Sd_wr_inst:	sd_wr
		generic map
		(
			BLOCK_LEN_LOG2	=>	BLOCK_LEN_LOG2,
			FIFO_DEPTH_LOG2	=>	FIFO_DEPTH_LOG2
		)
		port map
		(
			clk				=>	clk_sd,
			areset			=>	t_areset,
			init			=>	t_wr_init,
			read			=>	t_wr_read,
			readm			=>	t_wr_readm,
			dataaddr		=>	t_dataaddr,
			autoreread		=>	t_autoreread,
			sc_buzy			=>	t_sc_buzy,
			sc_q			=>	t_sc_q,
			rr_buzy			=>	t_rr_buzy,
			rr_content		=>	t_rr_content,
			rr_crcerr		=>	t_rr_crcerr,
			rd_buzy			=>	t_rd_buzy,
			rd_crcerr		=>	t_rd_crcerr,
			wrusedw			=>	t_wrusedw,
			sd_cmd			=>	sd_cmd,
			sd_data			=>	sd_data,
			buzy			=>	t_wr_buzy,
			cardready		=>	t_cardready,
			sc_send			=>	t_sc_send,
			sc_cmdno		=>	t_sc_cmdno,
			sc_content		=>	t_sc_content,
			rr_recv			=>	t_rr_recv,
			rr_longresp		=>	t_rr_longresp,
			rr_cmd			=>	t_rr_cmd,
			rd_recv			=>	t_rd_recv,
			rd_data			=>	t_rd_data,
--------------- for debug ---------------------
--			ostat			=>	owr_stat,
-----------------------------------------------
			aclr			=>	t_aclr
		);
	
	Sendcmd_inst: sendcmd
		port map
		(
			clk			=>	clk_sd,
			areset		=>	t_areset,
			send		=>	t_sc_send,
			cmdno		=>	t_sc_cmdno,
			content		=>	t_sc_content,
			buzy		=>	t_sc_buzy,
-------- for debug ---------------
--			ocnt:		out integer range 0 to 39;
--			ocmd:		out std_logic_vector( 39 downto 0 );
--			ocrc:		out std_logic_vector( 6 downto 0 );
------------------------------------
			q			=>	t_sc_q
		);
	
	Recvresp_inst: recvresp
		port map
		(
			clk			=>	clk_sd,
			areset		=>	t_areset,
			recv		=>	t_rr_recv,
			longresp	=>	t_rr_longresp,
			cmd			=>	t_rr_cmd,
			buzy		=>	t_rr_buzy,
			content		=>	t_rr_content,
	---------- for debug ----------------
	--		ocnt:		out integer range 0 to 126;
	--		ocrc:		out std_logic_vector( 6 downto 0 );
	-------------------------------------
			crcerr		=>	t_rr_crcerr
		);
	
	Recvdata_inst: recvdata 
		generic map
		(
			BLOCK_LEN_LOG2	=>	BLOCK_LEN_LOG2
		)
		port map
		(
			clk		=>	clk_sd,
			areset	=>	t_areset,
			recv	=>	t_rd_recv,
			data	=>	t_rd_data,
			buzy	=>	t_rd_buzy,
			crcerr	=>	t_rd_crcerr,
			wrreq	=>	t_wrreq,
------------- for debug -------------------
--			obitcnt:	out integer range 0 to 7;
--			ocnt:		out integer range 0 to 4095;
--			ocrc:		out std_logic_vector( 15 downto 0 );
-------------------------------------------
			q		=>	t_rd_q
		);
	
	Dcfifo_sd_inst: dcfifo_sd
		port map
		(
			aclr	=>	t_aclr,
			data	=>	t_rd_q,
			rdclk	=>	clk,
			rdreq	=>	t_rdreq,
			wrclk	=>	clk_sd,
			wrreq	=>	t_wrreq,
			q		=>	t_fifo_data,
			rdempty	=>	t_rdempty,
			rdusedw	=>	t_rdusedw,
			wrusedw	=>	t_wrusedw
		);
		
------------- for debug --------------
--	owr_buzy <= t_wr_buzy;
--	oreadm <= t_wr_readm;
--------------------------------------
	
end RTL;