library verilog;use verilog.vl_types.all;entity AOI_5_CA0 is    port(        y_out           : out    vl_logic;        x_in1           : in     vl_logic;        x_in2           : in     vl_logic;        x_in3           : in     vl_logic;        x_in4           : in     vl_logic;        x_in5           : in     vl_logic;        enable          : in     vl_logic    );end AOI_5_CA0;