library verilog;use verilog.vl_types.all;entity shift_reg is    port(        shiftreg        : out    vl_logic_vector(4 downto 0);        clock           : in     vl_logic;        reset           : in     vl_logic;        load            : in     vl_logic;        sel             : in     vl_logic_vector(1 downto 0);        data            : in     vl_logic_vector(4 downto 0)    );end shift_reg;