library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity divclk1 is    port(clk:in std_logic:='0';           divclk:out std_logic);end divclk1;architecture Behavioral of divclk1 issignal counter:std_logic_vector(5 downto 0):="000000";begin   process(clk)   begin      if clk'event and clk ='1' then         if(counter<="110001") then            counter<="000000";         else            counter<=counter+'1';         end if;   end if;   end process;   divclk<=counter(5);end Behavioral;