?? add2in_tb.vhd
字號:
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;use ieee.std_logic_arith.all;use std.TEXTIO.all;entity tb isend tb;architecture a_tb of tb is component Add2In port(D1:in std_logic_vector(7 downto 0); D2:in std_logic_vector(7 downto 0); Q: out std_logic_vector(8 downto 0); clk:in std_logic); end component; signal D1:std_logic_vector(7 downto 0):=(others=>'0'); signal D2:std_logic_vector(7 downto 0):=(others=>'0'); signal Q:std_logic_vector(8 downto 0); signal clk:std_logic:='0'; signal Dlatch:boolean:=false; signal SResult: integer; begin dut:Add2In port map(D1=>D1, D2=>D2, Q=>Q, clk=>clk); clk<=not clk after 20 us; process file InputD:text open read_mode is "TestData.dat"; variable DLine:LINE; variable good:Boolean; variable Data1:integer; variable Data2:integer; begin wait until clk='1' and clk'event; readline(InputD,DLine); read(DLine,Data1,good); read(Dline,Data2,good); if(good) then D1<=CONV_STD_LOGIC_VECTOR(Data1,8); D2<=CONV_STD_LOGIC_VECTOR(Data2,8); else assert false report"End of Reading INput File!" severity error; end if; end process; process file InputR:text open read_mode is "Result.dat"; variable RLine :LINE; variable Result:integer; begin wait until clk='1' and clk'event; Dlatch<=true; if Dlatch then readline(InputR,RLine); read(RLine,Result); SResult<=Result; if SResult/=Q then assert false report"Two values are different" severity warning; end if; end if; end process; end a_tb;
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