library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity divclk1_tb isend divclk1_tb;architecture behavior of divclk1_tb is	component divclk1	port(clk: in std_logic;			divclk: out std_logic);	end component;	signal clk:std_logic:='0';	signal divclk:std_logic;	begin	uut:divclk1 port map(		 clk=>clk,		 divclk=>divclk);		 clk<=not clk after 10ns;		end;