library verilog;use verilog.vl_types.all;entity sdr_sdram is    port(        clk             : in     vl_logic;        reset_n         : in     vl_logic;        addr            : in     vl_logic_vector(22 downto 0);        cmd             : in     vl_logic_vector(2 downto 0);        cmdack          : out    vl_logic;        datain          : in     vl_logic_vector(31 downto 0);        dataout         : out    vl_logic_vector(31 downto 0);        dm              : in     vl_logic_vector(3 downto 0);        sa              : out    vl_logic_vector(11 downto 0);        ba              : out    vl_logic_vector(1 downto 0);        cs_n            : out    vl_logic_vector(1 downto 0);        cke             : out    vl_logic;        ras_n           : out    vl_logic;        cas_n           : out    vl_logic;        we_n            : out    vl_logic;        dq              : inout  vl_logic_vector(31 downto 0);        dqm             : out    vl_logic_vector(3 downto 0)    );end sdr_sdram;