library verilog;use verilog.vl_types.all;entity mt48lc8m16a2 is    generic(        addr_bits       : integer := 12;        data_bits       : integer := 16;        col_bits        : integer := 9;        mem_sizes       : integer := 2097151;        tac             : real    := 6.000000;        thz             : real    := 7.000000;        toh             : real    := 2.700000;        tmrd            : real    := 2.000000;        tras            : real    := 44.000000;        trc             : real    := 66.000000;        trcd            : real    := 20.000000;        trp             : real    := 20.000000;        trrd            : real    := 15.000000;        twra            : real    := 7.500000;        twrp            : real    := 0.000000    );    port(        dq              : inout  vl_logic_vector;        addr            : in     vl_logic_vector;        ba              : in     vl_logic_vector(1 downto 0);        clk             : in     vl_logic;        cke             : in     vl_logic;        cs_n            : in     vl_logic;        ras_n           : in     vl_logic;        cas_n           : in     vl_logic;        we_n            : in     vl_logic;        dqm             : in     vl_logic_vector(1 downto 0)    );end mt48lc8m16a2;