?? ram.vhd
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library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.Numeric_Std.all;entity sync_ram1 is port ( clock : in std_logic; we,rd : in std_logic; address : in std_logic_vector(0 to 9); datain : in std_logic_vector(0 to 9); dataout : out std_logic_vector(0 to 9) );end sync_ram1;architecture RTL of sync_ram1 is type ram_type is array(0 to (2** address'length) -1) of std_logic_vector(datain'range); signal ram : ram_type; signal read_address : std_logic_vector(address'range);begin RamProc: process(clock) is begin if rising_edge(clock) then if we = '1' then ram(to_integer(unsigned(address))) <= datain; end if; read_address <= address; end if; if rd= '1' then dataout <= ram(to_integer(unsigned(read_address))); elsif rd='0' then dataout <="UUUUUUUUUU"; end if; end process RamProc;end architecture RTL;
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