library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.Numeric_Std.all;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity three is port(clock:in std_logic;dout:out std_logic_vector(9 downto 0) );end three;architecture struct of three is       signal x,y:std_logic_vector(9 downto 0);               component sync_ram1 is          port (    clock   : in  std_logic;    we,rd   : in  std_logic;    address : in  std_logic_vector(0 to 9);    datain  : in  std_logic_vector(0 to 9);    dataout : out std_logic_vector(0 to 9)  );end component;component counter is           port( clkIN : in std_logic;            count : out std_logic_vector(9 downto 0));end component;component lfsr_10 is    port(clk: in std_logic;    randout: buffer std_logic_vector(9 downto 0) ); end component;   begin      t1:lfsr_10 port map(clock,x);     t2:counter port map(clock,y);     t3:sync_ram1 port map(clock,'1','1',y,x,dout) ; end struct;