LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY cdecoder_3_8  IS
PORT (       d  : IN  STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ;
              G1 : IN  STD_LOGIC ;
        G2A, G2B : IN  STD_LOGIC ;
               q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ) ;
END ENTITY cdecoder_3_8 ;  -- VHDL 1993版可以這么用

ARCHITECTURE  rtl_cdecoder_3_8  OF  cdecoder_3_8  IS
BEGIN
    PROCESS ( d, G1, G2A, G2B )
    BEGIN
        IF ( G1= '1' AND G2A= '0' AND G2B = '0' ) THEN  -- 譯碼器的使能信號(hào)
                -- 采用CASE語句描述3-8譯碼電路
            CASE  d  IS  -- CASE語句的控制表達(dá)式是位矢量 d
                WHEN  "000"  =>  q <= "11111110" ;
                WHEN  "001"  =>  q <= "11111101" ;
                WHEN  "010"  =>  q <= "11111011" ;
                WHEN  "011"  =>  q <= "11110111" ;
                WHEN  "100"  =>  q <= "11101111" ;
                WHEN  "101"  =>  q <= "11011111" ;
                WHEN  "110"  =>  q <= "10111111" ;
                WHEN  "111"  =>  q <= "01111111" ;
                WHEN  OTHERS =>  q <= "XXXXXXXX" ;
            END CASE ;
        ELSE
            q <= "11111111" ;
        END IF ;
    END PROCESS ;
END ARCHITECTURE  rtl_cdecoder_3_8 ;