# Synplicity, Inc. constraint file
# C:\1553\syn\decoder_1554.sdc
# Written on Thu Dec 18 10:53:38 2003
# by Synplify Pro, 7.3.3      Scope Editor

#
# Clocks
#
define_clock            -name {dec_clk}  -freq 10.000 -clockgroup default_clkgroup

#
# Clock to Clock
#

#
# Inputs/Outputs
#
define_input_delay               -default  50.00 -ref {dec_clk:r}
define_output_delay              -default  50.00 -ref {dec_clk:r}
define_input_delay -disable      {rst_n}
define_output_delay -disable     {rx_csw}
define_input_delay -disable      {rx_data}
define_output_delay -disable     {rx_dval}
define_output_delay -disable     {rx_dw}
define_output_delay -disable     {rx_dword[0:15]}
define_output_delay -disable     {rx_perr}

#
# Registers
#

#
# Multicycle Path
#

#
# False Path
#
define_false_path           -from {p:rst_n} 

#
# Delay Path
#

#
# Attributes
#

#
# Other Constraints
#