#-- Synplicity, Inc.
#-- Version  7.5      
#-- Project file C:\1553\synthesis\EC\synplify\decoder_1553.prj
#-- Written on Sun Jun 27 18:46:33 2004


#add_file options
add_file -verilog "C:/1553_enc_dec/source/decoder_1553.v"
add_file -constraint "decoder_1553.sdc"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology LATTICE-EC
set_option -part LFEC20E
set_option -package F484C
set_option -speed_grade -4

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -top_module "decoder_1553"

#map options
set_option -frequency 8.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -force_gsr auto

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/decoder_1553.edn"

#implementation attributes
set_option -vlog_std v2001
impl -active "rev_1"