`include "inc.h"


//*******************************************************************************
//  S Y N T H E S I Z A B L E      S D R A M     C O N T R O L L E R    C O R E
//
//  This core adheres to the GNU Public License  
// 
//  This is a synthesizable Synchronous DRAM controller Core.  As it stands,
//  it is ready to work with 8Mbyte SDRAMs, organized as 2M x 32 at 100MHz
//  and 125MHz. For example: Samsung KM432S2030CT,  Fujitsu MB81F643242B.
//
//  The core has been carefully coded so as to be "platform-independent".  
//  It has been successfully compiled and simulated under three separate
//  FPGA/CPLD platforms:
//      Xilinx Foundation Base Express V2.1i
//      Altera Max+PlusII V9.21
//      Lattice ispExpert V7.0
//  
//  The interface to the host (i.e. microprocessor, DSP, etc) is synchronous
//  and supports only one transfer at a time.  That is, burst-mode transfers
//  are not yet supported.  In many ways, the interface to this core is much
//  like that of a typical SRAM.  The hand-shaking between the host and the 
//  SDRAM core is done through the "sdram_busy_l" signal generated by the 
//  core.  Whenever this signal is active low, the host must hold the address,
//  data (if doing a write), size and the controls (cs, rd/wr).  
//
//  Connection Diagram:
//  SDRAM side:
//  sd_wr_l                     connect to -WR pin of SDRAM
//  sd_cs_l                     connect to -CS pin of SDRAM
//  sd_ras_l                    connect to -RAS pin of SDRAM
//  sd_cas_l                    connect to -CAS pin of SDRAM
//  sd_dqm[3:0]                 connect to the DQM3,DQM2,DQM1,DQM0 pins
//  sd_ba[1:0]                  connect to BA1, BA0 pins of SDRAM
//  sd_addx[10:0]               connect to the Address bus [10:0]
//  sd_data[31:0]               connect to the data bus [31:0]
//  
//   
//  HOST side:
//  mp_addx[22:0]               connect to the address bus of the host. 
//                              23 bit address bus give access to 8Mbyte
//                              of the SDRAM, as byte, half-word (16bit)
//                              or word (32bit)
//  mp_data_in[31:0]            Unidirectional bus connected to the data out
//                              of the host. To use this, enable 
//                              "databus_is_unidirectional" in INC.H
//  mp_data_out[31:0]           Unidirectional bus connected to the data in 
//                              of the host.  To use this, enable
//                              "databus_is_unidirectional" in INC.H
//  mp_data[31:0]               Bi-directional bus connected to the host's
//                              data bus.  To use the bi-directionla bus,
//                              disable "databus_is_unidirectional" in INC.H
//  mp_rd_l                     Connect to the -RD output of the host
//  mp_wr_l                     Connect to the -WR output of the host
//  mp_cs_l                     Connect to the -CS of the host
//  mp_size[1:0]                Connect to the size output of the host
//                              if there is one.  When set to 0
//                              all trasnfers are 32 bits, when set to 1
//                              all transfers are 8 bits, and when set to
//                              2 all xfers are 16 bits.  If you want the
//                              data to be lower order aligned, turn on
//                              "align_data_bus" option in INC.H
//  sdram_busy_l                Connect this to the wait or hold equivalent
//                              input of the host.  The host, must hold the
//                              bus if it samples this signal as low.
//  sdram_mode_set_l            When a write occurs with this set low,
//                              the SDRAM's mode set register will be programmed
//                              with the data supplied on the data_bus[10:0].
//
//
//  Author:  Jeung Joon Lee  joon.lee@quantum.com,  cmosexod@ix.netcom.com
//  
//*******************************************************************************
//
//  Hierarchy:
//
//  SDRAM.V         Top Level Module
//  HOSTCONT.V      Controls the interfacing between the micro and the SDRAM
//  SDRAMCNT.V      This is the SDRAM controller.  All data passed to and from
//                  is with the HOSTCONT.
//  optional
//  MICRO.V         This is the built in SDRAM tester.  This module generates 
//                  a number of test logics which is used to test the SDRAM
//                  It is basically a Micro bus generator. 
//  
/*
*/ 



module sdcnt(	
		// system level stuff
			sys_rst_l,
			sys_clk,
		
		// SDRAM connections
			sd_wr_l,
		//    sd_cs_l,
			sd_ras_l,
			sd_cas_l,
			sd_dqm,
			
		// Host Controller connections
	    	//do_mode_set,
	  		do_read,
            do_write,
            //doing_refresh,
            sd_addx_mux,
            sd_addx10_mux,
            //sd_rd_ena,
           // sd_wr_ena,
      // modereg_cas_latency,
           // modereg_burst_length,
            //mp_data_mux,
			//decoded_dqm,
            do_write_ack,
            do_read_ack,
				doing_precharge,
				doing_refresh,
          //  do_modeset_ack,
           // pwrup,	 
				sd_busy_l,
				sddata_ena,

			// debug
            next_state
			//autorefresh_cntr,
			//autorefresh_cntr_l,
			//cntr_limit

		);

//parameter N1 = 4;

// ****************************************
//
//   I/O  DEFINITION
//
// ****************************************


// System level stuff
input	        sys_rst_l;
input	        sys_clk;

// SDRAM connections
output	        sd_wr_l;
//output	        sd_cs_l;
output	        sd_ras_l;
output	        sd_cas_l;
output	 [3:0]  sd_dqm;

// Host Controller connections
//input           do_mode_set;///////????????
input           do_read;
input           do_write;
//output          doing_refresh;
output  [1:0]   sd_addx_mux;
output  [1:0]   sd_addx10_mux;
//output          sd_rd_ena;
//output          sd_wr_ena;
//input   [2:0]   modereg_cas_latency;
//input   [2:0]   modereg_burst_length;
//output          mp_data_mux;
//input	[3:0]	decoded_dqm;
output          do_write_ack;
output          do_read_ack;
//output          do_modeset_ack;
//output			pwrup; 

// Debug
output  [4:0]   next_state;
//output	[3:0]	autorefresh_cntr;
//output			autorefresh_cntr_l;
//output	[1:0]	cntr_limit;
output sd_busy_l;
output doing_precharge;
output doing_refresh;
output sddata_ena;

// ****************************************
//
// Memory Elements 
//
// ****************************************
//
reg     [4:0]	next_state;
reg     [10:0]   refresh_timer;
reg 	        sd_wr_l;
//reg		        sd_cs_l;
reg		        sd_ras_l;
reg		        sd_cas_l;
reg     [3:0]   sd_dqm;
reg     [1:0]   sd_addx_mux;
reg     [1:0]   sd_addx10_mux;
//reg             sd_wr_ena;
reg		        pwrup;			// this variable holds the power up condition
reg     [1:0]  refresh_cntr;   // this is the refresh counter
reg				refresh_cntr_l;	// this is the refresh counter reset signal
reg     [8:0]   burst_length_cntr;
reg             burst_cntr_ena;
//reg             sd_rd_ena;      // read latch gate, active high
reg     [1:0]  cntr_limit;
//reg     [3:0]   modereg_burst_count;
reg     [2:0]   refresh_state;
//reg             mp_data_mux;
wire            do_refresh;     // this bit indicates autorefresh is due
reg             doing_refresh;  // this bit indicates that the state machine is 
                                // doing refresh.
reg     [3:0]   autorefresh_cntr;
reg             autorefresh_cntr_l;
reg             do_write_ack;
reg             do_read_ack;
//reg             do_modeset_ack;
reg             do_refresh_ack;

//reg  [12:0]  counter_wait;//counter used in initialization process to generate 100us delay
                        
reg  [13:0]  counter_wait;
//wire            Trc_expired, Ref_expired;	

//assign Trc_expired = (autorefresh_cntr == 4'h6); 			  
//assign Ref_expired = (refresh_cntr == cntr_limit);			 
reg doing_precharge;
reg sddata_ena;
assign sd_busy_l=~(do_write|do_read|doing_refresh);


//-----------------------------------------------------------------------------------------------------------------------------------
// State Machine
always @(posedge sys_clk or negedge sys_rst_l)
  if (~sys_rst_l) begin
    next_state	<= `state_wait;
    autorefresh_cntr_l <= `LO;
	refresh_cntr_l  <= `LO;
    pwrup       <= `HI;				// high indicates we've just power'd up or RESET
    sd_wr_l     <= `HI;
    //sd_cs_l     <= `HI;
    sd_ras_l    <= `HI;
    sd_cas_l    <= `HI;
    sd_dqm      <= 4'h0;
   // sd_wr_ena <= `LO;
    sd_addx_mux <= 2'b10;           // select the mode reg default value
    sd_addx10_mux <= 2'b11;         // select 1 as default
   // sd_rd_ena   <= `LO;
  //  mp_data_mux <= `LO;

    burst_cntr_ena <= `LO;          // do not enable the burst counter
    doing_refresh  <= `LO;
	 doing_precharge<= `LO;
    do_write_ack <= `LO;            // do not ack as reset default
    do_read_ack  <= `LO;            // do not ack as reset default
	 sddata_ena<=`LO;
   // do_modeset_ack <= `LO;          // do not ack as reset default
    do_refresh_ack <= `LO;
    counter_wait<=20'd0;
  end 
  else case (next_state)
//--------------------------------------------------------------------------------------------------------
    // Power Up state
   /* `state_powerup:  begin
        next_state  <= `state_precharge;
        sd_wr_l     <= `HI;
       // sd_cs_l     <= `HI;
    	sd_ras_l    <= `HI;
    	sd_cas_l    <= `HI;
        sd_dqm      <= 4'hF;
        sd_data_ena <= `LO;
        sd_addx_mux <= 2'b10;
        sd_rd_ena   <= `LO;
        pwrup       <= `HI;         // this is the power up run
        burst_cntr_ena <= `LO;      // do not enable the burst counter
		refresh_cntr_l <= `HI;		// allow the refresh cycle counter to count
     end*/

//-------------------------------------------------------------------------------------------------------------------
//Wait 100us
`state_wait: begin

		sd_wr_l     <= `HI;    //NOP       
    	sd_ras_l    <= `HI;   //NOP
    	sd_cas_l    <= `HI;   //NOP

      //sd_dqm      <= 4'hF;
		sd_dqm<=4'd0;
//		sd_wr_ena <= `LO;
		//sd_rd_ena   <= `LO;

		sd_addx_mux <= 2'b10;

	pwrup       <= `HI;   
	burst_cntr_ena <= `LO;      // do not enable the burst counter
	refresh_cntr_l <= `HI;		// allow the refresh cycle counter to count


	if(counter_wait>=14'd11000)   ////注意根據時鐘設定具體數值，對于105M的時鐘信號
	                              //等待100US需要10526個周期
											//但仿真結果表明至少要等到5555才能滿足100US的要求
	
  		 begin
  		 //調試屏蔽	next_state<=`state_precharge;
		    counter_wait<=14'd0;
		 	doing_precharge<=`HI; //下個周期進行PRECHARGE,
		   next_state<=`state_precharge;