//counter_wait<=13'd0;
			
		 end
	else  
		begin
     			counter_wait<=counter_wait+1;
                     next_state<=`state_wait;
              end
   end     

//---------------------------------------------------------------------------------------------------------------------------------------------------

    // PRECHARGE  all banks        	
    `state_precharge:  begin
       sd_wr_l     <= `LO;
       // sd_cs_l     <= `LO;
    	sd_ras_l    <= `LO;
    	sd_cas_l    <= `HI;

       //sd_dqm      <= 4'hF;
		 sd_dqm<=4'd0;
       sd_addx10_mux <= 2'b11;      // A10 = 1'b1   	 precharge all banks
	                            
	//	doing_precharge<= `LO;	 //下個周期PRECHARGE進行完畢

			if(sddata_ena)
				sddata_ena<=`LO;//關閉sddata總線的輸出
     // next_state<=`state_idle;				 // 對于50M的時鐘，20ns的間隔已經能夠滿足trp的要求，可以進入了idle狀態
       // if (do_write_ack)
           // do_write_ack<= `LO;         // done acknowledging the write request
        if (do_read_ack)
            do_read_ack <= `LO;         // done acknowledging the read request
		
		next_state  <= `state_precharge_dly;
    end  
//-----------------------------------------------------------------------------------------------------------------------------------
   /* // Delay Trp 
    // this delay is needed to meet the minimum precharge to new command
    // delay.  For most parts, this is 20nS, which means you need 1 clock cycle
    // of NOP at 100MHz
    `state_delay_Trp:  begin
        sd_wr_l     <= `HI;
        sd_cs_l     <= `HI;
      	sd_ras_l    <= `HI;
        if ( (refresh_cntr == cntr_limit) & (pwrup == `HI) ) begin
            doing_refresh <= `LO;                // refresh cycle is done
            refresh_cntr_l  <= `LO;             // ..reset refresh counter
            next_state <= `state_modeset;      // if this was power-up, then go and set mode reg
        end else begin
            doing_refresh <= `HI;        // indicate that we're doing refresh
            next_state	 <= `state_auto_refresh;
	    end
    end  */

//------------------------------------------------------------------------------------------------------------------
 //delay trp(precharge delay)
 //this delay is needed to meet the minimum precharge to new command
 // delay.  For most parts, this is 20nS, which means you need 1 clock cycle
 // of NOP at 100MHz
																										
 	

    `state_precharge_dly:
       begin
          sd_wr_l     <= `HI;
          //sd_cs_l     <= `HI;
      	 sd_ras_l    <= `HI;

       	 doing_precharge<=`LO;		//PRECHARGE finished

          next_state	 <= `state_idle;	   
       end  

 

//--------------------------------------------------------------------------------------------------------------------
    // Autorefresh
    `state_auto_refresh: begin
       sd_wr_l     <= `HI;
       // sd_cs_l     <= `LO;
    	sd_ras_l    <= `LO;
    	sd_cas_l    <= `LO;
        sd_addx10_mux <= 2'b01;      // A10 = 0   
        next_state  <= `state_auto_refresh_dly;
        autorefresh_cntr_l  <= `HI;  //allow refresh delay cntr (Trc) to tick
        do_refresh_ack <= `HI;      // acknowledge refresh request
     end    

//-------------------------------------------------------------------------------------------------------------------

    //  Trc delay.(Auto Refersh delay)
    // this delay is the delay from the refresh command to the next valid command
    // most parts require this to be 60 to 70nS.  So at 100MHz, we need at least
    // 6 NOPs.  
	 
    `state_auto_refresh_dly:  begin
          sd_wr_l     <= `HI;
        //  sd_cs_l     <= `HI;
          sd_ras_l    <= `HI;
          sd_cas_l    <= `HI;
          sd_addx10_mux <= 2'b00;      // select ROW again A10 = A20   

        // Wait for Trc
	 //if Trc has expired, new command can be sent to sdram
        if (autorefresh_cntr == 4'h6) 
		         begin  
              autorefresh_cntr_l <= `LO;  // reset Trc delay counter
              // Check if the number of specified back-back refreshes are done
              if (refresh_cntr == cntr_limit)   begin  
                   doing_refresh <= `LO;             // refresh cycle is done
                   refresh_cntr_l  <= `LO;           // reset refresh counter
                   // if this is not a power-up sequence, and there are pending 
                   // requests, then service it.
                   if (~pwrup)
                      if (do_write | do_read)
                          next_state <= `state_set_ras; // go service a pending read or write if any
                      else
                          next_state <= `state_idle;    // if there are no peding RD or WR, then go to idle state

                   // if this is part of power-up sequencing, we need to go and
                   // set mode register.
                   else
                      next_state <= `state_modeset;
              end 
        
              // IF refresh cycles not done yet, keep issuing autorefresh commands
             else
                   next_state <= `state_auto_refresh; 
           end


        // If Trc has not expired
        else begin
              next_state <= `state_auto_refresh_dly;
              do_refresh_ack <= `LO;
        end

    end
//---------------------------------------------------------------------------------------------------------------------------------------

    // MODE SET state
    `state_modeset:  begin
        next_state  <= `state_idle;
        sd_wr_l     <= `LO;
        //sd_cs_l     <= `LO;
        sd_ras_l    <= `LO;
        sd_cas_l    <= `LO;
        sd_addx_mux <= 2'b10;//set mode register
        sd_addx10_mux <= 2'b10;//set mode register
        doing_refresh <= `LO;   // deassert 
        if (pwrup)
           pwrup    <= `LO;                 // ..no more in power up mode
        //if (do_mode_set)
           // do_modeset_ack <= `LO;
    end

//--------------------------------------------------------------------------------------------------------------------------------------

    // IDLE state
    `state_idle:  begin
        sd_wr_l     <= `HI;
        //sd_cs_l     <= `HI;
        sd_ras_l	<= `HI;
        sd_cas_l	<= `HI;
  //      sd_wr_ena <= `LO;         // turn off the data bus drivers
     //   mp_data_mux <= `LO;         // drive the SD data bus with normal data  ？？？
        sd_addx_mux <= 2'b00;   // select ROW (A[19:10]) of mp_addx to SDRAM，and bank 
        sd_addx10_mux <= 2'b00; // select ROW (A[20])    "      "

        // if we've just come out of system reset (or powerup)
        // then we need to go and do initialization sequence.
        // Or, if a refresh is requested, go and service it.
        if (do_refresh | pwrup) begin
           doing_refresh <= `HI;        // indicate that we're doing refresh
           refresh_cntr_l <= `HI;		// allow refresh cycle counter to count up
           next_state <= `state_auto_refresh;
	    end

        // if a single word rad or write request is pending, go and service it
 		else if (do_write | do_read )          
           next_state <= `state_set_ras;  ///active  bank and row

        // if a mode register set is requested, go and service it//這種情況應該不會出現，因為set mode register的上一個狀態是autorefresh

        /*
	else if (do_mode_set) begin
           do_modeset_ack <= `HI;  // acknowledge the mode set request
           next_state <= `state_modeset;
           doing_refresh <= `HI;		// techincally we're not doing refresh, but 
        end                             // this signal is used to prevent the do_write be deasserted
        								// by the mode_set command.
        */
    end    


//-------------------------------------------------------------------------------------------------------------------------

    // SET RAS state   作用相當于active
    `state_set_ras:  begin
       // sd_cs_l     <= `LO;     // enable SDRAM 
        sd_ras_l    <= `LO;     // enable the RAS
		  
		   next_state  <= `state_ras_dly;   // wait for a bit

    end

//----------------------------------------------------------------------------------------------------------------------
    // RAS delay state.  
    // This delay is needed to meet Trcd delay.  This is the RAS to CAS delay.
    // for most parts this is 20nS.  So for 100MHz operation, there needs to be 
    // at least 1 NOP cycle.
	 //這里 ras delay=18ns,對于105M需要1個周期延時
    `state_ras_dly:  begin
       // sd_cs_l     <= `HI;     // disable SDRAM 
        sd_ras_l    <= `HI;     // disble the RAS
        sd_addx_mux <= 2'b01;   // select COLUMN 為下一個狀態提供列地址和bANK地址,注意對于全頁猝發寫入，列地址應該為全零
        sd_addx10_mux <= 2'b01; // select COLUMN 為下一個狀態提供列地址

        if (do_write)  begin
   //         sd_wr_ena <= `HI;     // turn on  the data bus drivers
           // sd_dqm      <= decoded_dqm;  // masks the data which is meant to be////
				 sd_dqm<=4'h0;
				 do_write_ack<= `HI;     //  下一個周期寫數據有效，提前打開AD_FIFO
	
				 //burst_cntr_ena <= `HI;      // enable the burst lenght counter
            //next_state  <= `state_write;      // if write, do the write  
				next_state  <= `state_write_delay;      // if write, do the write     
        end else begin
            sd_dqm      <= 4'h0;
            next_state  <= `state_set_cas;    // if read, do the read
        end
    end
//--------------------------------------------------------------
		`state_write_delay:		 //將寫命令延時一個周期發出，等待sddata_in數據有效
									
			begin
				sd_ras_l<=`HI;// no operation
				sd_cas_l<=`HI;// no operation
				sd_wr_l <=`HI;// no operation
				sd_dqm      <= 4'h0;

				burst_cntr_ena <= `HI;      // enable the burst lenght counter
            next_state  <= `state_write;      // if write, do the write   


		end

//------------------------------------------------------------------------------------------------------------
    /*
    // WRITE state
    `state_write:  begin
        sd_cs_l     <= `LO;     // enable SDRAM 
        sd_cas_l    <= `LO;     // enable the CAS
        sd_wr_l     <= `LO;     // enable the write
        do_write_ack<= `HI;     // acknowledge the write request
        sd_dqm      <= 4'hF;///?????
        next_state  <= `state_delay_Tras1;
    end

    `state_delay_Tras1:  begin  //功能不明

        sd_wr_l     <= `HI;
        sd_cs_l     <= `HI;
        sd_ras_l	<= `HI;
        sd_cas_l	<= `HI;
        sd_dqm      <= 4'hF;
        sd_addx_mux <= 2'b00;   // send ROW (A[19:10]) of mp_addx to SDRAM 
        sd_addx10_mux <= 2'b00; // send ROW (A[20])    "      "
        mp_data_mux <= `HI;         // drive the SD data bus with all zeros
        next_state  <= `state_delay_Tras2;
    end

    `state_delay_Tras2:  begin
        next_state  <= `state_precharge;
    end   
   */
//-------------------------------------------------------------------------------------------------------

//state write   //全頁猝發寫入  
`state_write:
	begin
		sd_cas_l <=`LO;
		sd_wr_l  <=`LO;
	//	do_write_ack<= `HI;     // acknowledge the write request
		sddata_ena<=`HI;		  //控制sddata總線輸出
		sd_dqm      <= 4'h0;
                             //對于全頁猝發 列地址應該為全零!!!!!
		 next_state  <= `state_write_wait;

		 
             

	end

//-----------------------------------------------------------------------------------------------------

//state write wait   //等待寫猝發結束 ！！！
`state_write_wait:
	begin
			sd_wr_l     <= `HI;  //NOP        	
        	sd_ras_l	<= `HI;  //NOP
        	sd_cas_l	<= `HI;  //NOP
		   sd_dqm      <= 4'h0;