?? sdc.v
字號(hào):
`include "inc.h"
module sdc(
// SYSTEM LEVEL CONNECTIONS
sys_rst_l,
sys_clk,
// SDRAM CONNECTIONS
sd_wr_l,
//sd_cs_l,
sd_ras_l,
sd_cas_l,
sd_dqm,
sd_addx,
sd_ba,
mp_addx,
do_write,
do_read,
sd_busy_l,
do_read_ack,
do_write_ack,
doing_precharge,
doing_refresh,
sddata_ena,
next_state
);
// ****************************************
//
// I/O DEFINITION
//
// ****************************************
// SYSTEM LEVEL CONNECTIONS
input sys_clk; // global system clock. Runs the sdram state machine
input sys_rst_l; // global active low asynchronous system reset
// SDRAM CONNECTIONS
output sd_wr_l; // SDRAM active low WRITE signal
//output sd_cs_l; // SDRAM active low chip select signal
output sd_ras_l; // SDRAM active low RAS
output sd_cas_l; // SDRAM active low CAS
output [3:0] sd_dqm; // SDRAM data masks
output [10:0] sd_addx; // SDRAM multiplexed address bus
//inout [31:0] sd_data; // SDRAM birectional data bus 32 bit
output [1:0] sd_ba; // SDRAM bank address , aka A11
input [20:0] mp_addx; // HOST address bus. 23 bits for 8Mb 21 bits for 2M
//input mp_rd_l; // HOST active low READ
//input mp_wr_l; // HOST active low WRITE
input do_write;
input do_read;
//input mp_cs_l; // HOST active low chip select
//input sdram_mode_set_l;
//input [1:0] mp_size; // 00=32bits, 10=16bits, 01=8bits
//`endif
output sd_busy_l;
output do_read_ack;
output do_write_ack;
output [4:0] next_state;
//output [31:0] sd_data_out;
//output sd_data_ena;
output doing_precharge;
output doing_refresh;
output sddata_ena;
//debug
//output do_write;
//output do_read;
// DEBUG
/*
`ifdef show_debug
output [31:0] mp_data_out_sd;
output mp_data_gate;
output do_write;
output [20:0] reg_mp_addx;
//output [31:0] reg_mp_data_mux;
output sd_addx_mux;
output sd_addx10_mux;
output do_modeset;
output do_read;
output doing_refresh;
output [3:0] next_state;
//output [12:0] autorefresh_cntr;
//output autorefresh_cntr_l;
output pwrup;
//output [3:0] top_state;
output [7:0] wr_cntr;
//output[31:0] mp_data_micro;
output [31:0] mp_data_out;
//output mp_data_mux;
//output sd_data_ena;
output sd_rd_ena;
`endif */
// INTER-MODULE CONNECTIONS
//wire do_modeset;
wire do_read;
wire do_write;
//wire doing_refresh;
//wire sd_addx_ena;
wire [1:0] sd_addx_mux;
wire [1:0] sd_addx10_mux;
//wire sd_rd_ena;
//wire sd_data_ena;
wire [4:0] next_state;
//wire [31:0] mp_data_out_sd;
//wire [31:0] mp_data_in;
//wire [31:0] mp_data_out;
//wire [31:0] sd_data;
//wire mp_cs_l;
//wire mp_wr_l;
//wire mp_rd_l;
//wire pwrup;
wire do_write_ack;
wire do_read_ack;
//wire do_modeset_ack;
//wire [31:0] reg_mp_data_mux;
//wire [31:0] sd_data_in;
//wire [31:0] sd_data_out;
//wire [31:0] reg_sd_data;
//wire sdram_mode_set_l;
wire sys_clk;
wire sd_busy_l;
wire doing_precharge;
wire doing_refresh;
wire sddata_ena;
// assign mp_data_out = mp_data_gate ? mp_data_out_sd : 32'hffffffff; ////
// `endif
// --- Bi-Directional Data bus Mode
/*`else
`ifdef simulate_mp
assign mp_data = mp_data_gate ? mp_data_out_sd : mp_simulator_data;
`else
bufif1 m0 (mp_data[0], mp_data_out_sd[0], mp_data_gate);
bufif1 m1 (mp_data[1], mp_data_out_sd[1], mp_data_gate);
bufif1 m2 (mp_data[2], mp_data_out_sd[2], mp_data_gate);
bufif1 m3 (mp_data[3], mp_data_out_sd[3], mp_data_gate);
bufif1 m4 (mp_data[4], mp_data_out_sd[4], mp_data_gate);
bufif1 m5 (mp_data[5], mp_data_out_sd[5], mp_data_gate);
bufif1 m6 (mp_data[6], mp_data_out_sd[6], mp_data_gate);
bufif1 m7 (mp_data[7], mp_data_out_sd[7], mp_data_gate);
bufif1 m8 (mp_data[8], mp_data_out_sd[8], mp_data_gate);
bufif1 m9 (mp_data[9], mp_data_out_sd[9], mp_data_gate);
bufif1 m10 (mp_data[10], mp_data_out_sd[10], mp_data_gate);
bufif1 m11 (mp_data[11], mp_data_out_sd[11], mp_data_gate);
bufif1 m12 (mp_data[12], mp_data_out_sd[12], mp_data_gate);
bufif1 m13 (mp_data[13], mp_data_out_sd[13], mp_data_gate);
bufif1 m14 (mp_data[14], mp_data_out_sd[14], mp_data_gate);
bufif1 m15 (mp_data[15], mp_data_out_sd[15], mp_data_gate);
bufif1 m16 (mp_data[16], mp_data_out_sd[16], mp_data_gate);
bufif1 m17 (mp_data[17], mp_data_out_sd[17], mp_data_gate);
bufif1 m18 (mp_data[18], mp_data_out_sd[18], mp_data_gate);
bufif1 m19 (mp_data[19], mp_data_out_sd[19], mp_data_gate);
bufif1 m20 (mp_data[20], mp_data_out_sd[20], mp_data_gate);
bufif1 m21 (mp_data[21], mp_data_out_sd[21], mp_data_gate);
bufif1 m22 (mp_data[22], mp_data_out_sd[22], mp_data_gate);
bufif1 m23 (mp_data[23], mp_data_out_sd[23], mp_data_gate);
bufif1 m24 (mp_data[24], mp_data_out_sd[24], mp_data_gate);
bufif1 m25 (mp_data[25], mp_data_out_sd[25], mp_data_gate);
bufif1 m26 (mp_data[26], mp_data_out_sd[26], mp_data_gate);
bufif1 m27 (mp_data[27], mp_data_out_sd[27], mp_data_gate);
bufif1 m28 (mp_data[28], mp_data_out_sd[28], mp_data_gate);
bufif1 m29 (mp_data[29], mp_data_out_sd[29], mp_data_gate);
bufif1 m30 (mp_data[30], mp_data_out_sd[30], mp_data_gate);
bufif1 m31 (mp_data[31], mp_data_out_sd[31], mp_data_gate);
assign mp_data_in = mp_data;
`endif
*/
//`endif
//
// SDRAM side bidirectional data bus drivers
//assign sd_data = sd_data_ena ? sd_data_out : 32'hzzzzzzzz; //
//
//
/*
bufif1 b0 (sd_data[0], sd_data_out[0], sd_data_ena);
bufif1 b1 (sd_data[1], sd_data_out[1], sd_data_ena);
bufif1 b2 (sd_data[2], sd_data_out[2], sd_data_ena);
bufif1 b3 (sd_data[3], sd_data_out[3], sd_data_ena);
bufif1 b4 (sd_data[4], sd_data_out[4], sd_data_ena);
bufif1 b5 (sd_data[5], sd_data_out[5], sd_data_ena);
bufif1 b6 (sd_data[6], sd_data_out[6], sd_data_ena);
bufif1 b7 (sd_data[7], sd_data_out[7], sd_data_ena);
bufif1 b8 (sd_data[8], sd_data_out[8], sd_data_ena);
bufif1 b9 (sd_data[9], sd_data_out[9], sd_data_ena);
bufif1 b10 (sd_data[10], sd_data_out[10], sd_data_ena);
bufif1 b11 (sd_data[11], sd_data_out[11], sd_data_ena);
bufif1 b12 (sd_data[12], sd_data_out[12], sd_data_ena);
bufif1 b13 (sd_data[13], sd_data_out[13], sd_data_ena);
bufif1 b14 (sd_data[14], sd_data_out[14], sd_data_ena);
bufif1 b15 (sd_data[15], sd_data_out[15], sd_data_ena);
bufif1 b16 (sd_data[16], sd_data_out[16], sd_data_ena);
bufif1 b17 (sd_data[17], sd_data_out[17], sd_data_ena);
bufif1 b18 (sd_data[18], sd_data_out[18], sd_data_ena);
bufif1 b19 (sd_data[19], sd_data_out[19], sd_data_ena);
bufif1 b20 (sd_data[20], sd_data_out[20], sd_data_ena);
bufif1 b21 (sd_data[21], sd_data_out[21], sd_data_ena);
bufif1 b22 (sd_data[22], sd_data_out[22], sd_data_ena);
bufif1 b23 (sd_data[23], sd_data_out[23], sd_data_ena);
bufif1 b24 (sd_data[24], sd_data_out[24], sd_data_ena);
bufif1 b25 (sd_data[25], sd_data_out[25], sd_data_ena);
bufif1 b26 (sd_data[26], sd_data_out[26], sd_data_ena);
bufif1 b27 (sd_data[27], sd_data_out[27], sd_data_ena);
bufif1 b28 (sd_data[28], sd_data_out[28], sd_data_ena);
bufif1 b29 (sd_data[29], sd_data_out[29], sd_data_ena);
bufif1 b30 (sd_data[30], sd_data_out[30], sd_data_ena);
bufif1 b31 (sd_data[31], sd_data_out[31], sd_data_ena);
*/
//assign sd_data_in = sd_data;
//
// INSTANTIATE THE SDRAM STATE MACHINE
//
sdcnt MYSDRAMCNT(
// system level stuff
.sys_rst_l(sys_rst_l),
.sys_clk(sys_clk),
// SDRAM connections
.sd_wr_l(sd_wr_l),
// .sd_cs_l(sd_cs_l),
.sd_ras_l(sd_ras_l),
.sd_cas_l(sd_cas_l),
.sd_dqm(sd_dqm),
// Host Controller connections
// .do_mode_set(do_modeset),
.do_read(do_read),
.do_write(do_write),
//.doing_refresh(doing_refresh),
.sd_addx_mux(sd_addx_mux),
.sd_addx10_mux(sd_addx10_mux),
//.sd_rd_ena(),
//.sd_wr_ena(sd_data_ena),
// .modereg_cas_latency(modereg_cas_latency),
// .modereg_burst_length(modereg_burst_length),
//.mp_data_mux(mp_data_mux),
// .decoded_dqm(decoded_dqm),
.do_write_ack(do_write_ack),
.do_read_ack(do_read_ack),
.doing_precharge(doing_precharge),
.doing_refresh(doing_refresh),
// .do_modeset_ack(do_modeset_ack),
//.pwrup(pwrup),
.sd_busy_l(sd_busy_l),
.sddata_ena(sddata_ena), //sddata三態(tài)總線輸出控制信號(hào)
// debug
.next_state(next_state)
//.autorefresh_cntr(autorefresh_cntr),
//.autorefresh_cntr_l(autorefresh_cntr_l)
);
//
// INSTANTIATE THE HOST INTERFACE LOGIC
//
hostcont MYHOSTCONT(
// system connections
//.sys_rst_l(sys_rst_l),
//.sys_clk(sys_clk),
// microprocessor side connections
.mp_addx(mp_addx),
//.mp_data_in(mp_data_in),
// .mp_data_out(mp_data_out_sd),
//.mp_data_out(mp_data_out),
//.mp_rd_l(mp_rd_l),
//.mp_wr_l(mp_wr_l),
//.sd_busy_l(sd_busy_l),
// SDRAM side connections
.sd_addx(sd_addx),
// .sd_data_in(sd_data_in),
//.sd_data_out(sd_data_out),
.sd_ba(sd_ba),
// SDRAMCNT side
.sd_addx10_mux(sd_addx10_mux),
.sd_addx_mux(sd_addx_mux)
// .sd_rd_ena(sd_rd_ena)
//.do_read(do_read),
//.do_write(do_write),
//.doing_refresh(doing_refresh),
// .modereg_burst_length(),
//.pwrup(pwrup),
//.do_write_ack(do_write_ack),
// .do_read_ack(do_read_ack)
);
endmodule
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