?? wr_rd.v
字號:
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:07:21 01/18/06
// Design Name:
// Module Name: sdram_wr_rd
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module wr_rd(clk,sd_data_in,lwr,ads,blast,do_read_ack,do_write_ack,pci_data,do_write,do_read,addr,sd_data_out,sd_rst
//debug
//,next_state
);
input clk;
input lwr;
input ads;
input blast;
input do_read_ack;
input do_write_ack;
input [31:0] sd_data_in;
//output wr_l,rd_l;
output do_write;
output do_read;
output [20:0] addr;
output [31:0] sd_data_out;
output sd_rst;
//debug
//output [3:0] next_state;
inout [31:0] pci_data;
//reg wr_l;
//reg rd_l;
reg do_write;
reg do_read;
reg sd_rst;
reg [31:0] sd_data_out;
reg [31:0] sd_data_in_reg;
reg [20:0] addr;
reg [31:0] reg_data;
//reg [31:0] previous_data;
reg [3:0] next_state;
reg [3:0] read_counter;
reg [2:0] addrm;
reg [31:0] mem [7:0];
reg [2:0] rst_counter;
//----------------------------------------------------------------
parameter idle = 4'd0,
reset = 4'd1,
// reset_wait = 4'd2,
write = 4'd3,
write_wait=4'd4,
send_read_cmd = 4'd5,
read_wait=4'd6,
burst_read=4'd7,
read_mem=4'd8;
//---------------------------------------------------------------------------------------------------
assign pci_data=((!lwr)&(!ads))? sd_data_in_reg : 32'hzzzzzzzz;//當pci端發出讀信號時，將數據輸出，否則呈現高阻，使數據輸入
always@(posedge clk)
begin
if(lwr&(!blast)) //每當pci寫入數據或命令時
begin
reg_data<=pci_data; // 將輸入的數據或命令寄存
//previous_data<=reg_data; // 與上一次的命令或數據對比
end
end
//--------------------------------------------------------------------------
always@(posedge clk)
begin
case(next_state)
idle:
begin
//wr_l<=1;
//rd_l<=1;
do_write<=1'b0;
do_read<=1'b0;
sd_rst<=1'b1;
read_counter<=4'd0;
rst_counter<=3'd0;
if(lwr&(!blast)) // 每當pci寫入數據或命令時
next_state<=write;
// begin
// if(pci_data==32'd0) // 寫入全0表示reset sdram,不完善
// if(lwr&(!blast)&(pci_data==32'd0))
//if(reg_data==32'd0)
//begin
// next_state<=reset;
// end
//else if(pci_data==32'h7fffeeee) //寫入2147479278發出讀命令
// else if(lwr&(!blast)&(pci_data==32'h7fffeeee))
// else if(reg_data==32'h7fffeeee)
// next_state<=send_read_cmd;
//else
// else if(lwr&(!blast)&(pci_data!=32'h7fffeeee)&(pci_data!=32'd0))
// next_state<=write; //其他情況為寫入數據
//end
else if((!lwr)&(!ads)) //當pci端發出讀信號時
next_state<=read_mem; //讀取寄存器
else next_state<=idle; //沒有讀或寫表示idle
end
reset:
begin
sd_rst<=1'b0;
addr<=21'd0;
//wr_l<=1;
//rd_l<=1;
do_write<=1'b0;
do_read<=1'b0;
sd_data_out<=32'd0;
addrm<=3'd0;
read_counter<=4'd0;
mem[0]<=32'd0;
mem[1]<=32'd0;
mem[2]<=32'd0;
mem[3]<=32'd0;
mem[4]<=32'd0;
mem[5]<=32'd0;
mem[6]<=32'd0;
mem[7]<=32'd0;
if(rst_counter==3'd5) //將rst信號維持低電平的時間維持5個周期
begin
rst_counter<=3'd0;
next_state<=idle;
end
else
begin
rst_counter<=rst_counter+1;
next_state<=reset;
end
//next_state<=reset_wait;
end
// -----------------------------------------------------------
/* reset_wait: //將reset延長一個時鐘周期
begin
sd_rst<=0;
addr<=21'd0;
//wr_l<=1;
//rd_l<=1;
do_write<=0;
do_read<=0;
sd_data_out<=32'd0;
addrm<=3'd0;
read_counter<=4'd0;
mem[0]<=32'd0;
mem[1]<=32'd0;
mem[2]<=32'd0;
mem[3]<=32'd0;
mem[4]<=32'd0;
mem[5]<=32'd0;
mem[6]<=32'd0;
mem[7]<=32'd0;
next_state<=idle;
end
*/
//---------------------------------------------------------------------------
write: //可能要加入等待周期
begin
sd_rst<=1'b1;
if(reg_data==32'd0)
begin
sd_rst<=1'b0;
next_state<=reset;
end
else if(reg_data==32'h7fffeeee) //寫入2147479278發出讀命令
next_state<=send_read_cmd;
else
begin
//wr_l<=0; //發出寫命令
do_write<=1'b1; //發出寫命令
sd_data_out<=reg_data; //向sdram發出數據
if(addr==21'd7) //發出地址
addr<=21'd0;
else addr<=addr+1;
next_state<=write_wait;
end
end
write_wait:
begin
sd_rst<=1'b1;
//調試屏蔽wr_l<=1; //不需要一直為低
sd_data_out<=sd_data_out; //保持輸出數據不變
//addr<=addr; //保持地址不變
if(do_write_ack)
begin
//wr_l<=1;
do_write<=1'b0;
next_state<=idle;
end
else next_state<=write_wait;
end
send_read_cmd: //可能要加入等待周期
begin
sd_rst<=1'b1;
//rd_l<=0; //send read command
do_read<=1'b1; //send read command
addr<=21'd0; //給出猝發讀的初始地址
//if(addr==7)
//addr<=21'd0;
//else addr<=addr+1;
//sd_data_in_reg<=sd_data_in;
//next_state<=idle;
next_state<=read_wait;
end
read_wait: //等待數據有效
begin
sd_rst<=1;
//調試屏蔽 rd_l<=1; //不需要一直為低
//addr<=addr;//地址保持
if(do_read_ack) //當收到do_read_ack后表示下一個周期數據有效，開始接受數據
begin
//rd_l<=1;
do_read<=1'b0;
next_state<=burst_read;
end
else next_state<=read_wait;
end
burst_read: //將sdram的數據寫道存儲器mem中
begin
sd_rst<=1'b1;
//rd_l<=1;
do_read<=1'b0;
if(addrm==3'd7)
addrm<=3'd0;
else
begin
addrm<=addrm+1;
mem[addrm]<=sd_data_in;
end
if(read_counter==4'd8)
begin
read_counter<=1'b0;
next_state<=idle;
end
else
begin
read_counter<=read_counter+1;
next_state<=burst_read;
end
end
read_mem:
begin
sd_rst<=1'b1;
//rd_l<=1;
do_read<=1'b0;
if(addrm==3'd7)
addrm<=3'd0;
else
begin
addrm<=addrm+1;
sd_data_in_reg<=mem[addrm]; //sd_data_in_reg是pci_data的輸出寄存器
end
next_state<=idle;
end
default:next_state<=idle;
endcase
end
endmodule
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