////////////////////////////////////////////////////////////////////////////////// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.//////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  /    Vendor: Xilinx// \   \   \/     Version: H.40//  \   \         Application: netgen//  /   /         Filename: sdc_synthesis.v// /___/   /\     Timestamp: Sat Mar 25 21:22:50 2006// \   \  /  \ //  \___\/\___\//             // Command	: -intstyle ise -w -ofmt verilog -sim sdc.ngc sdc_synthesis.v // Device	: xc3s400-4-pq208// Input file	: sdc.ngc// Output file	: sdc_synthesis.v// # of Modules	: 1// Design Name	: sdc// Xilinx	: D:/Xilinx//             // Purpose:    //     This verilog netlist is a verification model and uses simulation //     primitives which may not represent the true implementation of the //     device, however the netlist is functionally correct and should not //     be modified. This file cannot be synthesized and should only be used //     with supported simulation tools.//             // Reference:  //     Development System Reference Guide, Chapter 23//     Synthesis and Verification Design Guide, Chapter 6//             ////////////////////////////////////////////////////////////////////////////////`timescale 1 ns/1 psmodule sdc (  do_read, sys_rst_l, do_write, sys_clk, sd_busy_l, sd_wr_l, sd_ras_l, do_read_ack, doing_precharge, sd_data_ena, doing_refresh, do_write_ack, sd_cas_l, mp_addx, sd_ba, sd_addx, sd_dqm, next_state);  input do_read;  input sys_rst_l;  input do_write;  input sys_clk;  output sd_busy_l;  output sd_wr_l;  output sd_ras_l;  output do_read_ack;  output doing_precharge;  output sd_data_ena;  output doing_refresh;  output do_write_ack;  output sd_cas_l;  input [20 : 0] mp_addx;  output [1 : 0] sd_ba;  output [10 : 0] sd_addx;  output [3 : 0] sd_dqm;  output [4 : 0] next_state;  wire sd_busy_l_OBUF;  wire do_read_IBUF;  wire \MYSDRAMCNT/sd_wr_l ;  wire sys_rst_l_IBUF;  wire \MYSDRAMCNT/sd_ras_l ;  wire \MYSDRAMCNT/do_read_ack ;  wire \MYSDRAMCNT/doing_precharge ;  wire \MYSDRAMCNT/sd_wr_ena ;  wire \MYSDRAMCNT/doing_refresh ;  wire do_write_IBUF;  wire \MYSDRAMCNT/do_write_ack ;  wire \MYSDRAMCNT/sd_cas_l ;  wire mp_addx_0_IBUF;  wire sys_clk_BUFGP;  wire mp_addx_2_IBUF;  wire mp_addx_1_IBUF;  wire sd_ba_1_OBUF;  wire sd_ba_0_OBUF;  wire sd_addx_10_OBUF;  wire sd_addx_9_OBUF;  wire sd_addx_8_OBUF;  wire sd_addx_7_OBUF;  wire sd_addx_6_OBUF;  wire sd_addx_5_OBUF;  wire sd_addx_4_OBUF;  wire sd_addx_3_OBUF;  wire sd_addx_2_OBUF;  wire sd_addx_1_OBUF;  wire sd_addx_0_OBUF;  wire \MYSDRAMCNT/counter_wait_inst_sum_5 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_16 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_17 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_16 ;  wire mp_addx_20_IBUF;  wire mp_addx_19_IBUF;  wire mp_addx_18_IBUF;  wire mp_addx_17_IBUF;  wire mp_addx_16_IBUF;  wire mp_addx_15_IBUF;  wire mp_addx_14_IBUF;  wire mp_addx_13_IBUF;  wire mp_addx_12_IBUF;  wire mp_addx_11_IBUF;  wire mp_addx_10_IBUF;  wire mp_addx_9_IBUF;  wire mp_addx_8_IBUF;  wire mp_addx_7_IBUF;  wire mp_addx_6_IBUF;  wire mp_addx_5_IBUF;  wire mp_addx_4_IBUF;  wire mp_addx_3_IBUF;  wire sd_dqm_0_OBUF;  wire N0;  wire \MYSDRAMCNT/N39 ;  wire N891;  wire \MYSDRAMCNT/N69 ;  wire \MYSDRAMCNT/N64 ;  wire \MYSDRAMCNT/N76 ;  wire \MYSDRAMCNT/N43 ;  wire \MYSDRAMCNT/N2 ;  wire \MYSDRAMCNT/N22 ;  wire \MYSDRAMCNT/N68 ;  wire \MYSDRAMCNT/N26 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_14 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_15 ;  wire \MYSDRAMCNT/N70 ;  wire \MYSDRAMCNT/do_refresh_ack ;  wire \MYSDRAMCNT/refresh_state_FFd1 ;  wire \MYSDRAMCNT/_n0001 ;  wire \MYSDRAMCNT/_n0003 ;  wire \MYSDRAMCNT/_n0004 ;  wire \MYSDRAMCNT/_n0005 ;  wire \MYSDRAMCNT/_n0006 ;  wire \MYSDRAMCNT/_n0012 ;  wire \MYSDRAMCNT/_n0007 ;  wire \MYSDRAMCNT/_n0013 ;  wire \MYSDRAMCNT/_n0008 ;  wire \MYSDRAMCNT/_n0014 ;  wire \MYSDRAMCNT/_n0009 ;  wire \MYSDRAMCNT/_n0020 ;  wire \MYSDRAMCNT/_n0015 ;  wire \MYSDRAMCNT/_n0016 ;  wire \MYSDRAMCNT/_n0017 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_10 ;  wire \MYSDRAMCNT/_n0018 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_9 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_11 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_10 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_10 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_13 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_9 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_9 ;  wire \MYSDRAMCNT/_n0029 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_11 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_14 ;  wire \MYSDRAMCNT/refresh_cntr_l ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_8 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_8 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_1 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_12 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_12 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_13 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_0 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_17 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_15 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_18 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_19 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_16 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_18 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_5 ;  wire \MYSDRAMCNT/refresh_state_FFd1-In ;  wire \MYSDRAMCNT/counter_wait_inst_sum_7 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_3 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_11 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_1 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_0 ;  wire \MYSDRAMCNT/counter_wait_inst_inv_1 ;  wire \MYSDRAMCNT/counter_wait_inst_inv_0 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_7 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_7 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_3 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_2 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_2 ;  wire \MYSDRAMCNT/autorefresh_cntr_l ;  wire \MYSDRAMCNT/counter_wait_inst_sum_1 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_0 ;  wire \MYSDRAMCNT/_n0018_rt ;  wire \MYSDRAMCNT/counter_wait_inst_cy_2 ;  wire \MYSDRAMCNT/_n0077 ;  wire \MYSDRAMCNT/burst_cntr_ena ;  wire \MYSDRAMCNT/pwrup ;  wire \MYSDRAMCNT/counter_wait_inst_sum_12 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_8 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_13 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_6 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_14 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_6 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_15 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_18 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_19 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_17 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_3 ;  wire \MYSDRAMCNT/counter_wait_inst_cy_4 ;  wire \MYSDRAMCNT/burst_length_cntr_0_N0 ;  wire \MYSDRAMCNT/refresh_cntr_0_N0 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_4 ;  wire \MYSDRAMCNT/N10 ;  wire \MYSDRAMCNT/autorefresh_cntr_0_N0 ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_19 ;  wire \MYSDRAMCNT/counter_wait_inst_sum_4 ;  wire \MYSDRAMCNT/sdcnt_burst_length_cntr__n0000<7>_cyo ;  wire \MYSDRAMCNT/N4 ;  wire \MYSDRAMCNT/sdcnt__n0022<0>_cyo ;  wire \MYSDRAMCNT/sdcnt__n0022<1>_cyo ;  wire \MYSDRAMCNT/sdcnt__n0022<2>_cyo ;  wire \MYSDRAMCNT/sdcnt__n0022<3>_cyo ;  wire \MYSDRAMCNT/sdcnt__n0022<4>_cyo ;  wire \MYSDRAMCNT/sdcnt__n0022<5>_cyo ;  wire \MYSDRAMCNT/sdcnt__n0022<6>_cyo ;  wire \MYSDRAMCNT/sdcnt__n0022<7>_cyo ;  wire \MYSDRAMCNT/sdcnt__n0022<8>_cyo ;  wire \MYSDRAMCNT/counter_wait_inst_lut3_5 ;  wire \MYSDRAMCNT/And_cyo ;  wire \MYSDRAMCNT/N5 ;  wire \MYSDRAMCNT/nor_cyo ;  wire \MYSDRAMCNT/And_cyo1 ;  wire \MYSDRAMCNT/N6 ;  wire \MYSDRAMCNT/nor_cyo1 ;  wire \MYSDRAMCNT/And_cyo2 ;  wire \MYSDRAMCNT/N7 ;  wire \MYSDRAMCNT/nor_cyo2 ;  wire \MYSDRAMCNT/N8 ;  wire \MYSDRAMCNT/N9 ;  wire \MYSDRAMCNT/sdcnt_burst_length_cntr__n0000<0>_cyo ;  wire \MYSDRAMCNT/sdcnt_burst_length_cntr__n0000<1>_cyo ;  wire \MYSDRAMCNT/sdcnt_burst_length_cntr__n0000<2>_cyo ;  wire \MYSDRAMCNT/sdcnt_burst_length_cntr__n0000<3>_cyo ;  wire \MYSDRAMCNT/sdcnt_burst_length_cntr__n0000<4>_cyo ;  wire \MYSDRAMCNT/sdcnt_burst_length_cntr__n0000<5>_cyo ;  wire \MYSDRAMCNT/sdcnt_burst_length_cntr__n0000<6>_cyo ;  wire \MYSDRAMCNT/counter_wait_inst_cy_6 ;  wire N11;  wire N3;  wire N916;  wire N903;  wire N12;  wire N13;  wire N15;  wire N16;  wire N17;  wire \MYSDRAMCNT/_n0008_MUXF5 ;  wire N907;  wire CHOICE1772;  wire CHOICE1717;  wire \MYSDRAMCNT/refresh_timer_6_rt ;  wire CHOICE1806;  wire CHOICE1685;  wire CHOICE1746;  wire CHOICE1815;  wire CHOICE1677;  wire CHOICE1704;  wire N900;  wire CHOICE1781;  wire N884;  wire N908;  wire \MYSDRAMCNT/refresh_timer_7_rt ;  wire CHOICE1735;  wire CHOICE1659;  wire CHOICE1725;  wire \MYSDRAMCNT/burst_length_cntr_4_rt ;  wire \MYSDRAMCNT/burst_length_cntr_7_rt ;  wire CHOICE1660;  wire \MYSDRAMCNT/burst_length_cntr_2_rt ;  wire \MYSDRAMCNT/refresh_timer_8_rt ;  wire CHOICE1744;  wire CHOICE1752;  wire N886;  wire CHOICE1782;  wire N882;  wire CHOICE1809;  wire \MYSDRAMCNT/refresh_timer_5_rt ;  wire N918;  wire N887;  wire CHOICE1726;  wire \MYSDRAMCNT/burst_length_cntr_1_rt ;  wire CHOICE1789;  wire \MYSDRAMCNT/counter_wait_6_rt ;  wire N914;  wire \MYSDRAMCNT/burst_length_cntr_6_rt ;  wire CHOICE1716;  wire \MYSDRAMCNT/counter_wait_14_rt ;  wire \MYSDRAMCNT/burst_length_cntr_5_rt ;  wire CHOICE1951;  wire CHOICE1826;  wire N880;  wire \MYSDRAMCNT/burst_length_cntr_8_rt ;  wire CHOICE1981;  wire CHOICE1945;  wire CHOICE1933;  wire CHOICE1913;  wire CHOICE1975;  wire CHOICE1829;  wire CHOICE1931;  wire CHOICE1988;  wire CHOICE1932;  wire CHOICE1906;  wire CHOICE1992;  wire N878;  wire \MYSDRAMCNT/_n0016_MUXF5 ;  wire N460;  wire N461;  wire \MYSDRAMCNT/_n0016_MUXF51 ;  wire N462;  wire \MYSDRAMCNT/_n0016_MUXF6 ;  wire CHOICE1871;  wire \MYSDRAMCNT/burst_length_cntr_3_rt ;  wire CHOICE1897;  wire CHOICE1885;  wire CHOICE1998;  wire N905;  wire CHOICE1836;  wire N910;  wire CHOICE1955;  wire CHOICE1907;  wire CHOICE1967;  wire \MYSDRAMCNT/refresh_timer_4_rt ;  wire \MYSDRAMCNT/counter_wait_9_rt ;  wire \MYSDRAMCNT/refresh_timer_9_rt ;  wire CHOICE1898;  wire \MYSDRAMCNT/refresh_timer_3_rt ;  wire CHOICE1845;  wire CHOICE1887;  wire N912;  wire CHOICE1979;  wire CHOICE1985;  wire CHOICE2008;  wire CHOICE2006;  wire CHOICE1916;  wire CHOICE1878;  wire CHOICE1864;  wire CHOICE1843;  wire CHOICE1886;  wire CHOICE1994;  wire \MYSDRAMCNT/refresh_timer_1_rt ;  wire \MYSDRAMCNT/refresh_timer_2_rt ;  wire \MYSDRAMCNT/next_state_4_1 ;  wire \MYSDRAMCNT/next_state_0_1 ;  wire \MYSDRAMCNT/next_state_1_1 ;  wire \MYSDRAMCNT/next_state_1_2 ;  wire N920;  wire N921;  wire N922;  wire N923;  wire N924;  wire N925;  wire N926;  wire N927;  wire N928;  wire N929;  wire N930;  wire N931;  wire N932;  wire N933;  wire N934;  wire N935;  wire N936;  wire [1 : 0] \MYSDRAMCNT/sd_addx10_mux ;  wire [1 : 0] \MYSDRAMCNT/sd_addx_mux ;  wire [4 : 0] \MYSDRAMCNT/next_state ;  wire [1 : 0] \MYSDRAMCNT/refresh_cntr ;  wire [19 : 0] \MYSDRAMCNT/counter_wait ;  wire [3 : 0] \MYSDRAMCNT/autorefresh_cntr ;  wire [8 : 0] \MYSDRAMCNT/burst_length_cntr ;  wire [4 : 0] \MYSDRAMCNT/_n0002 ;  wire [9 : 0] \MYSDRAMCNT/refresh_timer ;  wire [9 : 1] \MYSDRAMCNT/_n0022 ;  wire [9 : 0] \MYSDRAMCNT/_n0021 ;  wire [1 : 0] \MYSDRAMCNT/_n0010 ;  wire [3 : 0] \MYSDRAMCNT/autorefresh_cntr__n0000 ;  wire [1 : 0] \MYSDRAMCNT/_n0011 ;  wire [8 : 1] \MYSDRAMCNT/burst_length_cntr__n0000 ;  wire [1 : 0] \MYSDRAMCNT/refresh_cntr__n0000 ;  defparam \MYSDRAMCNT/_n0010<1> .INIT = 16'hABA8;  LUT4 \MYSDRAMCNT/_n0010<1>  (    .I0(\MYSDRAMCNT/sd_addx_mux [1]),    .I1(\MYSDRAMCNT/next_state [0]),    .I2(\MYSDRAMCNT/next_state [4]),    .I3(N11),    .O(\MYSDRAMCNT/_n0010 [1])  );  defparam \sd_addx<1>1 .INIT = 16'h7564;  LUT4 \sd_addx<1>1  (    .I0(\MYSDRAMCNT/sd_addx_mux [0]),    .I1(\MYSDRAMCNT/sd_addx_mux [1]),    .I2(mp_addx_1_IBUF),    .I3(mp_addx_9_IBUF),    .O(sd_addx_1_OBUF)  );  GND XST_GND (    .G(sd_dqm_0_OBUF)  );  VCC XST_VCC (    .P(N0)  );