////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 7.1.04i
//  \   \         Application : 
//  /   /         Filename : clksys.v
// /___/   /\     Timestamp : 01/26/2007 10:00:02
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: clksys
//
// Module clksys
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps

module clksys(CLKIN_IN, 
              CLKFX_OUT, 
              CLKFX180_OUT, 
              CLK0_OUT, 
              LOCKED_OUT);

    input CLKIN_IN;
   output CLKFX_OUT;
   output CLKFX180_OUT;
   output CLK0_OUT;
   output LOCKED_OUT;
   
   wire CLKFB_IN;
   wire CLKFX_BUF;
   wire CLK0_BUF;
   wire GND;
   
   assign GND = 0;
   assign CLK0_OUT = CLKFB_IN;
   BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), 
                         .O(CLKFX_OUT));
   BUFG CLK0_BUFG_INST (.I(CLK0_BUF), 
                        .O(CLKFB_IN));
   // Period Jitter (unit interval) for block DCM_INST = 0.10 UI
   // Period Jitter (Peak-to-Peak) for block DCM_INST = 0.94 ns
   DCM DCM_INST (.CLKFB(CLKFB_IN), 
                 .CLKIN(CLKIN_IN), 
                 .DSSEN(GND), 
                 .PSCLK(GND), 
                 .PSEN(GND), 
                 .PSINCDEC(GND), 
                 .RST(GND), 
                 .CLKDV(), 
                 .CLKFX(CLKFX_BUF), 
                 .CLKFX180(CLKFX180_OUT), 
                 .CLK0(CLK0_BUF), 
                 .CLK2X(), 
                 .CLK2X180(), 
                 .CLK90(), 
                 .CLK180(), 
                 .CLK270(), 
                 .LOCKED(LOCKED_OUT), 
                 .PSDONE(), 
                 .STATUS());
   // synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
   // synthesis attribute CLKDV_DIVIDE of DCM_INST is "2.000000"
   // synthesis attribute CLKFX_DIVIDE of DCM_INST is "10"
   // synthesis attribute CLKFX_MULTIPLY of DCM_INST is "21"
   // synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
   // synthesis attribute CLKIN_PERIOD of DCM_INST is "20.000000"
   // synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
   // synthesis attribute DESKEW_ADJUST of DCM_INST is "SYSTEM_SYNCHRONOUS"
   // synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
   // synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
   // synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
   // synthesis attribute FACTORY_JF of DCM_INST is "C080"
   // synthesis attribute PHASE_SHIFT of DCM_INST is "0"
   // synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
   // synopsys translate_off
   defparam DCM_INST.CLK_FEEDBACK = "1X";
   defparam DCM_INST.CLKDV_DIVIDE = 2.000000;
   defparam DCM_INST.CLKFX_DIVIDE = 10;
   defparam DCM_INST.CLKFX_MULTIPLY = 21;
   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
   defparam DCM_INST.CLKIN_PERIOD = 20.000000;
   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
   defparam DCM_INST.FACTORY_JF = 16'hC080;
   defparam DCM_INST.PHASE_SHIFT = 0;
   defparam DCM_INST.STARTUP_WAIT = "FALSE";
   // synopsys translate_on
endmodule