`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    10:53:35 03/03/06
// Design Name:    
// Module Name:    top
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module top(	clk50in,
				addata,
		      pcilwr,
     			pciblast,
        		pciads,

				wr,
				ras,
				cas,
				dqm,
				sd_addr,
				sd_ba,
				clkAD,
				clk_sd,
				pcidata,
				sddata
				//debug
			//	,empty
			,sddataout_reg1
				,full

				);

input   clk50in;
//input	 [7:0] addata;
input	 [15:0] addata;		 //雙通道采集
input	  pcilwr;
input	  pciblast;
input	  pciads;

output  wr;
output  ras;
output  cas;
output  [3:0] dqm;
output  [10:0] sd_addr;
output  [1:0] sd_ba;
output  clkAD;
output clk_sd;

inout [31:0] pcidata;
inout [31:0] sddata;

//debug
//output empty;
output full;
output [31:0] sddataout_reg1;

wire clk_sys;
//wire clk100m;
wire clk50m;
wire sd_rst;
wire	FIFO_ad_wr;
wire	FIFO_ad_rd;
wire	ainit;
//wire	[7:0] adout;
//wire	[15:0] adout;
wire	[31:0] adout;	 // FIFO輸出數(shù)據(jù)
wire  [1:0] rd_count;

wire	doing_precharge;
wire	doing_refresh;
wire	 [31:0] sddataout;
wire	 [12:0] addr;
wire	 do_write;
wire	 do_read;
wire	 do_write_ack;
wire	 do_read_ack;

wire clk50ibufg;

wire sddata_ena;//三態(tài)總線sddata數(shù)據(jù)輸出控制信號(hào)
wire fifo_full;
reg full;



reg [15:0] addata_reg1,addata_reg2,addata_reg3,addata_reg4;
reg [31:0] sddata_in;  



reg ff1,ff2;





clkdcm mydcm (
    .CLKIN_IN(clk50in), 
    
	 .CLKFX_OUT(clk200m), 		
    .CLKFX180_OUT(clkAD), 	
    .CLKIN_IBUFG_OUT(clk50ibufg), 
    .CLK0_OUT(clk50m), 
    
    .LOCKED_OUT()
    );

	 clksys mysys (
    .CLKIN_IN(clk50ibufg),   
    .CLKFX_OUT(clk_sys), 	  //105M_sys
    .CLKFX180_OUT(clk_sd),   
    .CLK0_OUT(), 
    .LOCKED_OUT()
    );

always@(posedge clk200m or negedge sd_rst)	  
begin
	if(!sd_rst)	//異步復(fù)位
		begin
			

			addata_reg1<=16'd0;
			addata_reg2<=16'd0;
			addata_reg3<=16'd0;
			addata_reg4<=16'd0;
		end
	else
		begin
			addata_reg1<=addata;
			addata_reg2<=addata_reg1;
			addata_reg3<=addata_reg2;
			addata_reg4<=addata_reg3;
		end
end






always@(posedge clk200m or negedge sd_rst) 
begin
	if(!sd_rst)			 //異步復(fù)位
		begin
			ff1<=1'b0;
			ff2<=1'b0;
		end
	else
		begin
			ff1<=FIFO_ad_wr;
			ff2<=ff1;
		end
end




adfifo ADFF(
				
					.din(addata_reg4),
				
					.wr_en(ff2),
				
				
					.wr_clk(clk200m),
				
					.rd_en(FIFO_ad_rd),
					.rd_clk(clk_sys),
					
					.rst(ainit),
					.dout(adout),
					.full(fifo_full),
					.empty(),
					.rd_data_count(rd_count)
				      );


always@(posedge clk_sys or negedge sd_rst)
begin
	if(!sd_rst)
		
		full<=1'b0;
	else
	 	full<=fifo_full;
		
end
					




maincontrol mymain(
							.clk(clk_sys),
							.clk50m(clk50m),
							.rd_count(rd_count),
							.doing_precharge(doing_precharge), 						
							.doing_refresh(doing_refresh),
							.lwr(pcilwr),
							.blast(pciblast),
							.ads(pciads),
							.sd_data_out(sddataout),
						
							.sd_rst(sd_rst),
							.addr(addr),
							.do_write(do_write),
							.do_read(do_read),					 
							.do_write_ack(do_write_ack),
							.do_read_ack(do_read_ack),
							.ainit(ainit),
							.FIFO_ad_rd(FIFO_ad_rd),
							.FIFO_ad_wr(FIFO_ad_wr),
							.sddataout_reg1(sddataout_reg1),
							.pci_data(pcidata)
							);




sdc mysdcontrol(
 				.sys_rst_l(sd_rst),
            .sys_clk(clk_sys),
           
            .sd_wr_l(wr),           
            .sd_ras_l(ras),
            .sd_cas_l(cas),
            .sd_dqm(dqm),
            .sd_addx(sd_addr),
           

            .sd_ba(sd_ba),
           
            .mp_addx({addr[12:0],8'h00}),		 

            
          

				.do_write(do_write),
				.do_read(do_read),
         
            .sd_busy_l(),
	     		.do_read_ack(do_read_ack),
		  		.do_write_ack(do_write_ack),
		  		.doing_precharge(doing_precharge),
		  		.doing_refresh(doing_refresh),
				.sddata_ena(sddata_ena),	//sddata三態(tài)總線輸出控制信號(hào)
         
            .next_state()
		
			
					
					);

//--------------------------------------------
always@(posedge clk_sys or negedge sd_rst )	
	begin
		 if(!sd_rst)			//異步復(fù)位

		 	sddata_in<=32'd0;

	
		else sddata_in<=adout;
	end


assign sddata=(sddata_ena)?sddata_in:32'hzzzzzzzz;		//輸出數(shù)據(jù)的三態(tài)總線

assign  sddataout=sddata;




endmodule