數字鎖相環頂層設計
下面給出詳細描述DPLL的工作過程。
1．當環路失鎖時，異或門鑒相器比較輸入信號和輸出信號之間的相位差異，并產生K變模可逆計數器的計數方向控制信號。
2．K變模可逆計數器根據計數方向控制信號調整計數值，控制信號為高進行減計數，并當計數值到達0時，輸出借位脈沖信號；為低進行加計數，并當計數值達到預設的K模值時，輸出進位脈沖信號。
3．脈沖加減電路則根據進位脈沖信號和借位脈沖信號在電路輸出信號中進行脈沖的增加和扣除操作，來調整輸出信號的頻率。
4．重復上面的調整過程，當環路進入鎖定狀態時，異或門鑒相器的輸出為一占空比50%的方波，而K變模可逆計數器則周期性地產生進位脈沖輸出和借位脈沖輸出，導致脈沖加減電路的輸出周期性的加入和扣除半個脈沖[12]。
5.5.1數字鎖相環的頂層VHDL語言描述
library ieee;
use ieee.std_logic_1164.all; 
library work;
entity suoxiang is 
	port
	(v1 :  in  std_logic;
		cp1 :  in  std_logic;
		en :  in  std_logic;
		d :  in  std_logic;
		c :  in  std_logic;
		b :  in  std_logic;
		a :  in  std_logic;
		cp2 :  in  std_logic;
		clr :  in  std_logic;
		v2 :  out  std_logic);
end suoxiang;
architecture bdf_type of suoxiang is 
component clkdiv
generic (n:integer);
	port(clk : in std_logic;
		 clkout_3 : out std_logic);
end component;
component count_k port (clk : in std_logic; j : in std_logic;  en : in std_logic;
		 d : in std_logic; c : in std_logic;  b : in std_logic;
		 a : in std_logic; r1 : out std_logic;  r2 : out std_logic);
end component;
component id port (idclk : in std_logic;
		 clr : in std_logic;
		 inc : in std_logic;
		 dec : in std_logic;
		 iout : out std_logic);
end component;
signal	synthesized_wire_0 :  std_logic;
signal	synthesized_wire_1 :  std_logic;
signal	synthesized_wire_2 :  std_logic;
signal	synthesized_wire_3 :  std_logic;
signal	synthesized_wire_4 :  std_logic;
begin 
v2 <= synthesized_wire_0;
b2v_inst : clkdiv generic map(n => 3)
port map(clk => synthesized_wire_0, clkout_3 => synthesized_wire_2);
b2v_inst2 : count_k
port map(clk => cp1, j => synthesized_wire_1,
		 en => en, d => d, c => c, b => b, a => a,
		 r1 => synthesized_wire_3, r2 => synthesized_wire_4);
synthesized_wire_1 <= v1 xor synthesized_wire_2;
b2v_inst4 : id
port map(idclk => cp2,clr => clr, inc => synthesized_wire_3,
		 dec => synthesized_wire_4,
		 iout => synthesized_wire_0);
end;