module wave_gen_new(clk,fre_factor_low,fre_factor_hi,out1);
input clk;
input[15:0] fre_factor_low,fre_factor_hi;
wire[31:0] fre_factor;
assign fre_factor={fre_factor_hi,fre_factor_low};
output[11:0] out1;
//reg[11:0] out1;
/////////////////////////////////
reg[31:0] addr;
sin_rom rom1(
	.address(addr[31:22]),
	.clock(clk),
	.q(out1));
/////////////////////////////////
always @(posedge clk)
begin
	addr<=addr+fre_factor;
	//out1<=sin_data;
end

endmodule