{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 07 09:40:53 2007 " "Info: Processing started: Sun Jan 07 09:40:53 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sample -c sample --generate_symbol=F:\\young_ys\\zhsj\\zonghesheji\\young_ys\\sample\\sample.v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sample -c sample --generate_symbol=F:\\young_ys\\zhsj\\zonghesheji\\young_ys\\sample\\sample.v" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "sample.v(23) " "Warning (10268): Verilog HDL information at sample.v(23): Always Construct contains both blocking and non-blocking assignments" {  } { { "sample.v" "" { Text "F:/young_ys/zhsj/zonghesheji/young_ys/sample/sample.v" 23 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 07 09:40:53 2007 " "Info: Processing ended: Sun Jan 07 09:40:53 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}