library verilog;use verilog.vl_types.all;entity fifo1 is    generic(        DATA_WIDTH      : integer := 8;        ADDRESS_WIDTH   : integer := 6;        FIFO_DEPTH      : integer := 64    );    port(        data_out        : out    vl_logic_vector;        empty           : out    vl_logic;        full            : out    vl_logic;        data_in         : in     vl_logic_vector;        clk_read        : in     vl_logic;        read            : in     vl_logic;        clk_write       : in     vl_logic;        write           : in     vl_logic;        rst             : in     vl_logic    );end fifo1;