library verilog;use verilog.vl_types.all;entity GrayCounter_2 is    generic(        COUNTER_WIDTH   : integer := 7    );    port(        gray_out        : out    vl_logic_vector;        bin_addr        : out    vl_logic_vector;        enable          : in     vl_logic;        rst             : in     vl_logic;        clk             : in     vl_logic    );end GrayCounter_2;