?? da_tlc5620.asm.rpt
字號:
Assembler report for DA_TLC5620
Tue Jul 15 17:52:43 2008
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/WJ1C6/Logic design/Logic design/DA_TLC5620/DA_TLC5620/DA_TLC5620.sof
6. Assembler Device Options: C:/WJ1C6/Logic design/Logic design/DA_TLC5620/DA_TLC5620/DA_TLC5620.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Jul 15 17:52:43 2008 ;
; Revision Name ; DA_TLC5620 ;
; Top-level Entity Name ; DA_TLC5620 ;
; Family ; Cyclone ;
; Device ; EP1C6Q240C8 ;
+-----------------------+---------------------------------------+
+-----------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+--------------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+----------+---------------+
; Configuration device ; Epcs1 ; Auto ;
; Use smart compilation ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; JTAG user code for target device ; Ffffffff ; Ffffffff ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; JTAG user code for configuration device ; Ffffffff ; Ffffffff ;
; Configuration device auto user code ; Off ; Off ;
; Auto-increment JTAG user code for multiple configuration devices ; On ; On ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
+--------------------------------------------------------------------------------+----------+---------------+
+-------------------------------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------------------------------+
; File Name ;
+-------------------------------------------------------------------------+
; C:/WJ1C6/Logic design/Logic design/DA_TLC5620/DA_TLC5620/DA_TLC5620.sof ;
; C:/WJ1C6/Logic design/Logic design/DA_TLC5620/DA_TLC5620/DA_TLC5620.pof ;
+-------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/WJ1C6/Logic design/Logic design/DA_TLC5620/DA_TLC5620/DA_TLC5620.sof ;
+----------------+----------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------------------------------+
; Device ; EP1C6Q240C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x001050D9 ;
+----------------+----------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/WJ1C6/Logic design/Logic design/DA_TLC5620/DA_TLC5620/DA_TLC5620.pof ;
+----------------+----------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------------------------------+
; Device ; EPCS1 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x01593650 ;
+----------------+----------------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Tue Jul 15 17:52:42 2008
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DA_TLC5620 -c DA_TLC5620
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Jul 15 17:52:43 2008
Info: Elapsed time: 00:00:02
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