--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=10 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=13 SKIP_BITS=0 denominator numerator quotient remainder
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_abs 2006:01:02:19:20:00:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:05:17:10:06:16:SJ cbx_stratix 2006:05:17:09:28:32:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION alt_u_div_ote (denominator[9..0], numerator[12..0])
RETURNS ( den_out[9..0], quotient[12..0], remainder[9..0]);
FUNCTION add_sub_iac (cin, dataa[9..0], datab[9..0])
RETURNS ( result[9..0]);

--synthesis_resources = lut 41 
SUBDESIGN sign_div_unsign_4nh
( 
	denominator[9..0]	:	input;
	numerator[12..0]	:	input;
	quotient[12..0]	:	output;
	remainder[9..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_ote;
	adder : add_sub_iac;
	gnd_wire	: WIRE;
	norm_num[12..0]	: WIRE;
	protect_quotient[12..0]	: WIRE;
	protect_remainder[9..0]	: WIRE;

BEGIN 
	divider.denominator[] = denominator[];
	divider.numerator[] = norm_num[];
	adder.cin = gnd_wire;
	adder.dataa[] = denominator[];
	adder.datab[] = protect_remainder[];
	gnd_wire = B"0";
	norm_num[] = numerator[];
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	quotient[] = protect_quotient[];
	remainder[] = protect_remainder[];
END;
--VALID FILE