?? altsyncram_nn01.tdf
字號:
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cycloneiii_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/rom0_ROMDataTable_5c28aac1.hdl.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_WIDTH = 11,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 2047,
PORT_A_LOGICAL_RAM_DEPTH = 2048,
PORT_A_LOGICAL_RAM_WIDTH = 32,
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[10..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[10..0]);
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
END;
--VALID FILE
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