?? timer.vhd
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Timer is
generic(MAX : positive := 300); --timeout value
Port ( clk : in std_logic; --10Hz
start, reset : in std_logic; --starts the timer
timeout : out std_logic); --timer has timed out
end Timer;
architecture Behavioral of Timer is
signal count : natural range 0 to MAX;
begin
process(clk, reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
if start = '0' or count = MAX then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;
timeout <= '1' when count = MAX else '0';
end Behavioral;
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