module shifter(clk,m,co,s,d,qb,cn);
	input clk,m,co;
	input[1:0] s;
	input[7:0] d;
	output[7:0] qb;
	output cn;
	reg[7:0] qb;
	reg cn;
always@(clk)
	begin
		case(s)
		'b00:qb[7:0]=d[7:0];
		'b10:
			begin
				if(m)begin cn=d[7];qb[7:1]=d[6:0];qb[0]=co;end
				else begin qb[7:1]=d[6:0];qb[0]=d[7];end
			end
		'b01:
			begin
				if(m)begin cn=d[0];qb[6:0]=d[7:1];qb[7]=co;end
				else begin qb[6:0]=d[7:1];qb[7]=d[0];end
			end
		'b11:qb=d+co;
		endcase
	end
endmodule